Specifications

ManualsBrandsCypress ManualsComputer HardwareCY14B101P

CY14B101P

1-Mbit (128 K × 8) Serial SPI nvSRAM

with Real Time Clock

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-44109 Rev. *O Revised November 6, 2014

1-Mbit (128 K × 8) Serial SPI nvSRAM with Real Time Clock

Features

■ 1-Mbit nonvolatile static random access memory (nvSRAM)

❐ Internally organized as 128 K × 8

❐ STORE to QuantumTrap nonvolatile elements initiated

automatically on power-down (AutoStore) or by user using

HSB pin (Hardware STORE) or SPI instruction (Software

STORE)

❐ RECALL to SRAM initiated on power-up (Power-up

RECALL) or by SPI instruction (Software RECALL)

❐ Automatic STORE on power-down with a small capacitor

■ High reliability

❐ Infinite read, write, and RECALL cycles

❐ 1 million STORE cycles to QuantumTrap

❐ Data retention: 20 years

■ Real time clock (RTC)

❐ Full featured real time clock

❐ Watchdog timer

❐ Clock alarm with programmable interrupts

❐ Capacitor or battery backup for RTC

❐ Backup current of 0.35 µA (Typical)

■ High speed serial peripheral interface (SPI)

❐ 40 MHz clock rate - SRAM memory access

❐ 25 MHz clock rate - RTC memory access

❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)

■ Write protection

❐ Hardware protection using Write Protect (WP) pin

❐ Software protection using Write Disable instruction

❐ Software block protection for 1/4, 1/2, or entire array

■ Low power consumption

❐ Single 3 V +20%, –10% operation

❐ Average active current of 10 mA at 40 MHz operation

■ Industry standard configurations

❐ Industrial temperature

❐ 16-pin small outline integrated circuit (SOIC) package

❐ Restriction of hazardous substances (RoHS) compliant

Overview

The Cypress CY14B101P combines a 1-Mbit nonvolatile static

RAM with full featured real time clock in a monolithic integrated

circuit with serial SPI interface. The memory is organized as

128 K words of 8 bits each. The embedded nonvolatile elements

incorporate the QuantumTrap technology, creating the world’s

most reliable nonvolatile memory. The SRAM provides infinite

read and write cycles, while the QuantumTrap cells provide

highly reliable nonvolatile storage of data. Data transfers from

SRAM to the nonvolatile elements (STORE operation) takes

place automatically at power-down. On power-up, data is

restored to the SRAM from the nonvolatile memory (RECALL

operation). The STORE and RECALL operations can also be

initiated by the user through SPI instruction.

For a complete list of related documentation, click here.

Instruction

Address

Decoder

Data I/O register

Status Register

Power Control

STORE/RECALL

Control

Instruction decode

Write protect

Control logic

QuantumTrap

STORE

RECALL

SCK

CAP

HSB

128 K X 8

SRAM Array

128 K X 8

RTC

INT

MUX

A0-A16

D0-D7

HOLD

out

Logic Block Diagram

Not Recommended for New Designs

Summary of content (37 pages)

PAGE 1
CY14B101P 1-Mbit (128 K × 8) Serial SPI nvSRAM with Real Time Clock Features ■ ■ 1-Mbit nonvolatile static random access memory (nvSRAM) ❐ Internally organized as 128 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by user using HSB pin (Hardware STORE) or SPI instruction (Software STORE) ❐ RECALL to SRAM initiated on power-up (Power-up RECALL) or by SPI instruction (Software RECALL) ❐ Automatic STORE on power-down with a small capacitor ■ Write pr
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CY14B101P Pinout ................................................................................ 3 Pin Definitions .................................................................. 3 Device Operation .............................................................. 4 SRAM Write ................................................................. 4 SRAM Read ................................................................ 4 STORE Operation .......................................................
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CY14B101P Pinout NC 1 16 VCC VRTCbat 2 15 INT Xout 3 14 VCAP 13 SO Xin 4 Top View not to scale WP 5 12 SI HOLD 6 11 SCK VRTCcap 7 10 CS VSS 8 9 HSB Pin Definitions Pin Name I/O Type Description CS Input Chip select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low power standby mode. SCK Input Serial clock. Runs at speeds up to maximum of fSCK. Serial input is latched at the rising edge of this clock.
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CY14B101P CY14B101P is a 1-Mbit nvSRAM memory with integrated RTC and SPI interface. All the reads and writes to nvSRAM happen to the SRAM, which gives nvSRAM the unique capability to handle infinite writes to the memory. The data in SRAM is secured by a STORE sequence that transfers the data in parallel to the nonvolatile QuantumTrap cells. A small capacitor (VCAP) is used to AutoStore the SRAM data in nonvolatile cells when power goes down providing power-down data security.
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Figure 2 shows the proper connection of the storage capacitor (VCAP) for AutoStore operation. See DC Electrical Characteristics on page 24 for the size of the VCAP. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. The HSB pin must be left unconnected if not used. Figure 2. AutoStore Mode RECALL Operation VCC A RECALL operation transfers the data stored in the nonvolatile QuantumTrap elements to the SRAM.
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Serial Peripheral Interface Serial Clock (SCK) SPI Overview Serial clock is generated by the SPI master and the communication is synchronized with this clock after CS goes LOW. The SPI is a four-pin interface with Chip Select (CS), Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins. CY14B101P provides serial access to nvSRAM through SPI interface. The SPI bus on CY14B101P can run at speeds up to 40 MHz for all instructions except RDRTC which runs at 25 MHz.
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CY14B101P Figure 3. System Configuration Using SPI nvSRAM SCK M OSI SCK SI SO SCK SI SO u C o n tro lle r C Y14B 101P CS C Y14B 101P HO LD CS HO LD CS1 HO LD 1 CS2 HO LD 2 SPI Modes CY14B101P device may be driven by a microcontroller with its SPI peripheral running in either of those two modes: ■ SPI Mode 0 (CPOL=0, CPHA=0) ■ SPI Mode 3 (CPOL=1, CPHA=1) For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after CS goes active.
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CY14B101P Power-Up Power-up is defined as the condition when the power supply is turned on and VCC crosses VSWITCH voltage. During this time, the CS must be enabled to follow the VCC voltage. Therefore, CS must be connected to VCC through a suitable pull-up resistor. As a built in safety feature, CS is both edge sensitive and level sensitive. After power-up, the device is not selected until a falling edge is detected on CS. This ensures that CS is HIGH, before going LOW to start the first operation.
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CY14B101P Status Register The Status Register bits are listed in Table 2. The Status Register consists of a Ready bit (RDY) and data protection bits WEN, BP0, BP1, and WPEN. The RDY bit can be polled to check the Ready/Busy status while a nvSRAM STORE or Software RECALL cycle is in progress. The Status Register can be modified by WRSR instruction and read by RDSR instruction. However, only the WPEN, BP1 and BP0 bits of the Status Register can be modified by using the WRSR instruction.
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CY14B101P Figure 6. Read Status Register (RDSR) Instruction Timing CS 0 1 2 3 4 5 6 7 0 1 1 0 MSB 2 3 4 5 6 7 SI 0 0 0 0 0 1 0 HI-Z SO LSB D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Data Figure 7. Write Status Register (WRSR) Instruction Timing CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Data in Opcode SI SO 0 0 0 0 0 0 0 1 D7 X MSB X X D3 D2 X X LSB HI-Z Write Protection and Block Protection edge of CS.
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CY14B101P Write Disable instruction disables the write by clearing the WEN bit to ‘0’ in order to protect the device against inadvertent writes. This instruction is issued following the falling edge of CS followed by opcode for WRDI instruction. The WEN bit is cleared on the rising edge of CS following a WRDI instruction. Figure 9. WRDI Instruction CS 0 1 2 3 4 5 6 7 Table 5.
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CY14B101P address (0x1FFFF) is reached, the address rolls over to 0x0000 and the device continues to write. does not write any data to the protected memory. If the address roll over takes the burst write to unprotected space, it resumes writes. The same operation is true if a burst write is initiated within a write protected block. The WEN bit is reset to ‘0’ on completion of a WRITE sequence.
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CY14B101P Figure 13.
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CY14B101P WRITE RTC (WRTC) Instruction bytes of data. WRTC allows burst mode write operation. When writing more than one registers in burst mode, the address rolls over to 0x00 after the last RTC address (0x0F) is reached. WRITE RTC (WRTC) instruction allows the user to modify the contents of RTC registers. The WRTC instruction requires the WEN bit to be set to '1' before it can be issued. If WEN bit is '0', a WREN instruction needs to be issued before using WRTC.
PAGE 15
CY14B101P Figure 18. AutoStore Enable Operation CS 1 2 3 4 5 6 7 SCK SI 0 1 0 1 1 0 0 1 HI-Z SO Figure 20. HOLD Operation AutoStore Disable (ASDISB) instruction AutoStore is enabled by default in CY14B101P. The AutoStore Disable instruction disables the AutoStore on CY14B101P. This setting is not nonvolatile and needs to be followed by a STORE sequence if this is desired to survive the power cycle. To issue this instruction, the device must be write enabled (WEN = ‘1’).
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CY14B101P nvTIME Operation The CY14B101P offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. The RTC registers occupy a separate address space from nvSRAM and are accessible through the Read RTC register and Write RTC register sequence on register addresses 0x00 to 0x0F. Internal double buffering of the time keeping registers prevents accessing transitional internal clock data during a read or write operation.
PAGE 17
CY14B101P The value of OSCF must be reset to ‘0’ when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on. To reset OSCF, set the write bit ‘W’ (in the flags register at 0x00) to a ‘1’ to enable writes to the flags register. Write a ‘0’ to the OSCF bit and then reset the write bit to ‘0’ to disable writes.
PAGE 18
CY14B101P . Figure 21. Watchdog Timer Block Diagram Clock Divider Oscillator 32,768 KHz 1 Hz 32 Hz Counter Zero Compare WDF Load Register WDS Q D WDW Q write to Watchdog Register Watchdog Register Power Monitor The CY14B101P provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low VCC access.
PAGE 19
CY14B101P Accessing the Real Time Clock through SPI timekeeping registers to ensure that transitional values of time are not read. CY14B101P uses 16 registers for RTC. These registers can be read out or written to by accessing all 16 registers in burst mode or accessing each register, one at a time. The RDRTC and WRTC instructions are used to access the RTC. All the RTC registers can be read in burst mode by issuing the RDRTC instruction and reading all 16 bytes without bringing the CS pin HIGH.
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CY14B101P Table 8.
PAGE 21
CY14B101P Table 9. Register Map Detail Time Keeping - Years D7 D6 0x0F D5 D4 D3 D2 10s years D1 D0 Years Time Keeping - Months 0x0E D7 D6 D5 D4 0 0 0 10s month D3 D2 D1 D0 Months Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.
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CY14B101P Table 9. Register Map Detail (continued) WatchDog Timer D7 D6 WDS WDW D5 D4 D3 D2 D1 D0 WDT WDS Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0. WDW Watchdog write enable. Setting this bit to ‘1’ disables any WRITE to the watchdog timeout value (D5 – D0).
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CY14B101P Table 9. Register Map Detail (continued) Alarm - Seconds 0x02 D7 D6 D5 M D4 D3 10s alarm seconds D2 D1 D0 Alarm seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value. Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value.
PAGE 24
CY14B101P Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Maximum accumulated storage time Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount lead soldering temperature (3 Seconds) ...............................
PAGE 25
CY14B101P Data Retention and Endurance Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 20 Years 1,000 K Max Unit 6 pF 8 pF Test Conditions 16-pin SOIC Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 55.17 C / W 2.
PAGE 26
CY14B101P RTC Characteristics Parameter Description VRTCbat IBAK RTC battery pin voltage [14] RTC backup current VRTCcap[15] RTC capacitor pin voltage Min Typ[13] Max Units 1.8 3.0 3.6 V TA (min) – – 0.35 µA 25 °C – 0.35 – µA TA (max) – – 0.5 µA TA (min) 1.6 – 3.6 V 25 °C 1.5 3.0 TA (max) 1.4 3.6 V 3.
PAGE 27
CY14B101P Switching Waveforms Figure 25. Synchronous Data Timing (Mode 0) tCS CS tCH tCL tCSH SCK tSD SI tHD VALID IN VALID IN VALID IN tOH tCO SO HI-Z tHZCS HI-Z Figure 26. HOLD Timing ~ ~ CS SCK tHH tHH tSH tSH HOLD tHHZ tHLZ SO Document Number: 001-44109 Rev.
PAGE 28
CY14B101P AutoStore or Power-Up RECALL Over the Operating Range tFA [19] tSTORE CY14B101P Min Max – 20 Description Power-Up RECALL duration [20] STORE cycle duration – [21] Time allowed to complete SRAM write cycle tDELAY VSWITCH tVCCRISE [22] Low voltage trigger level VCC rise time Unit ms 8 ms – 25 ns – 150 2.65 – V µs 1.
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CY14B101P Software Controlled STORE/RECALL Cycles Over the Operating Range tRECALL tSS CY14B101P Description [25, 26] Unit Min Max RECALL duration – 200 µs Soft sequence processing time – 100 µs Switching Waveforms Figure 28. Software STORE Cycle [26] Figure 29. Software RECALL Cycle [26] CS CS 0 1 2 3 4 5 6 7 0 SCK SI 1 2 3 4 5 6 7 SCK 0 0 1 1 1 1 0 0 SI 0 1 1 0 0 0 0 0 tRECALL tSTORE HI-Z RWI RDY RDY Figure 30. AutoStore Enable Cycle Figure 31.
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CY14B101P Hardware STORE Cycle Over the Operating Range tPHSB CY14B101P Description Hardware STORE pulse width Min Max 15 – Unit ns Switching Waveforms Figure 32. Hardware STORE Cycle [27] Write Latch set ~ ~ tPHSB HSB (IN) tSTORE tHHHD ~ ~ tDELAY HSB (OUT) tLZHSB RWI tPHSB HSB (IN) HSB pin is driven HIGH to VCC only by Internal 100 K: resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. tDELAY RWI ~ ~ HSB (OUT) ~ ~ Write Latch not set Note 27.
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CY14B101P Ordering Information Ordering Code Package Diagram Package Type Operating Range 51-85022 16-pin SOIC Industrial CY14B101P-SFXI CY14B101P-SFXIT Ordering Code Definitions CY 14 B 101 P - SF X I T Option: T - Tape and Reel Blank - Std. Pb-free Temperature: I - Industrial (–40 to 85 °C) Package: SF - 16 SOIC P - Serial SPI nvSRAM with RTC Density: Voltage: B - 3.0 V 101 - 1 Mb 14 - nvSRAM Cypress Document Number: 001-44109 Rev.
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CY14B101P Package Diagram Not Recommended for New Designs Figure 33. 16-pin SOIC (0.413 × 0.299 × 0.0932 inches) Package Outline, 51-85022 51-85022 *E Document Number: 001-44109 Rev.
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CY14B101P Acronym Document Conventions Description Units of Measure BCD Binary Coded Decimal CPHA Clock Phase °C degree Celsius CPOL Clock Polarity F farad EEPROM Electrically Erasable Programmable Read-Only Memory Hz hertz kHz kilohertz k kilohm MHz megahertz A microampere mA milliampere F microfarad s microsecond ms millisecond ns nanosecond  ohm % percent pF picofarad ppm parts per million sec second V volt W watt EIA Electronic Industries Alliance
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CY14B101P Document Title: CY14B101P, 1-Mbit (128 K × 8) Serial SPI nvSRAM with Real Time Clock Document Number: 001-44109 Orig. of Submission Rev. ECN Description of Change Change Date ** 1939467 UNC / 01/16/2008 New data sheet.
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CY14B101P Document Title: CY14B101P, 1-Mbit (128 K × 8) Serial SPI nvSRAM with Real Time Clock Document Number: 001-44109 Orig. of Submission Rev. ECN Description of Change Change Date *E 2767333 GVCH 09/22/2009 Changed STORE cycles to QuantumTrap from 200K to 1 Million Updated Figure 2 Updated IBAK RTC backup current spec unit from nA to A Added Contents on page 2. *F 2893734 GVCH 03/17/10 Removed inactive part from Ordering Information table. Updated links in Sales, Solutions, and Legal Information.
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CY14B101P Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.
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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cypress Semiconductor: CY14B101P-SFXI CY14B101P-SFXIT