Specifications

CY14B101P
Document Number: 001-44109 Rev. *O Page 30 of 36
Hardware STORE Cycle
Over the Operating Range
Parameter Description
CY14B101P
Unit
Min Max
t
PHSB
Hardware STORE pulse width 15 – ns
Switching Waveforms
Figure 32. Hardware STORE Cycle
[27]
~
~
HSB (IN)
HSB (OUT)
RWI
HSB (IN)
HSB (OUT)
RWI
t
HHHD
t
STORE
t
PHSB
t
DELAY
t
LZHSB
t
DELAY
t
PHSB
HSB pin is driven HIGH to V
CC
only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
Write Latch not set
Write Latch set
~
~
~
~
~
~
Note
27. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Not Recommended for New Designs