1 Mbit nvSRAM Specification Sheet

PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
Document #: 001-50091 Rev. *A Page 15 of 22
AC Switching Characteristics
Cypress
Parameter
Alt.
Parameter
Description
40MHz
Unit
Min Max
f
SCK
f
SCK
Clock Frequency, SCK 40 MHz
t
CL
t
WL
Clock Pulse Width Low 11 ns
t
CH
t
WH
Clock Pulse Width High 11 ns
t
CS
t
CE
CS High Time 20 ns
t
CSS
t
CES
CS Setup Time 10 ns
t
CSH
t
CEH
CS Hold Time 10 ns
t
SD
t
SU
Data In Setup Time 5 ns
t
HD
t
H
Data In Hold Time 5 ns
t
HH
t
HD
HOLD Hold Time 5 ns
t
SH
t
CD
HOLD Setup Time 5 ns
t
CO
t
V
Output Valid 9 ns
t
HHZ
t
HZ
HOLD to Output High Z 15 ns
t
HLZ
t
LZ
HOLD to Output Low Z 15 ns
t
OH
t
HO
Output Hold Time 0 ns
t
HZCS
t
DIS
Output Disable Time 25 ns
Figure 21. Synchronous Data Timing (Mode 0)
Figure 22. HOLD
Timing
HI-Z
VALID IN
HI-Z
CS
SCK
SI
SO
t
CL
t
CH
t
CSS
t
SD
t
HD
t
CO
t
OH
t
CS
t
CSH
t
HZCS
CS
SCK
HOLD
SO
t
SH
t
HHZ
t
HLZ
t
HH
t
SH
t
HH
~
~
~
~
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