4-Mbit nvSRAM Specification Sheet

PRELIMINARY
CY14B104LA, CY14B104NA
Document #: 001-49918 Rev. *A Page 14 of 23
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.
[24, 25]
Parameters Description
20 ns 25 ns 45 ns
Unit
Min Max Min Max Min Max
t
RC
STORE/RECALL Initiation Cycle Time 20 25 45 ns
t
SA
Address Setup Time 0 0 0 ns
t
CW
Clock Pulse Width 152030 ns
t
HA
Address Hold Time 0 0 0 ns
t
RECALL
RECALL Duration 200 200 200 μs
Switching Waveforms
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle
[25]
Figure 13. AutoStore Enable/Disable Cycle
W
5&
W
5&
W
6$
W
&:
W
&:
W
6$
W
+$
W
/=&(
W
+=&(
W
+$
W
+$
W
+$
W
'(/$<
W
6725(
W
5(&$//
W
+++'
W
/=+6%
+LJK,PSHGDQFH
$GGUHVV $GGUHVV$GGUHVV
&(
2(
+6%6725(RQO\
'4'$7$
5:,
W
5&
W
5&
W
6$
W
&:
W
&:
W
6$
W
+$
W
/=&(
W
+=&(
W
+$
W
+$
W
+$
W
'(/$<
$GGUHVV $GGUHVV$GGUHVV
&(
2(
'4'$7$
5:,
W
66
Notes
24. The software sequence is clocked with CE
controlled or OE controlled reads.
25. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE
must be HIGH during all six consecutive cycles.
[+] Feedback