CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Features ■ 25 ns and 45 ns Access Times ■ Internally Organized as 512K x 8 (CY14B104K) or 256K x 16 (CY14B104M) ■ Hands Off Automatic STORE on Power Down with only a Small Capacitor ■ STORE to QuantumTrap Nonvolatile Elements is Initiated by Software, Device Pin, or AutoStore on Power Down ■ RECALL to SRAM is Initiated by Software or Power Up ■ High Reliability ■ Infinite Read, Write, and RECALL Cycles ■ 1 Million S
CY14B104K, CY14B104M Contents Features ...............................................................................1 Functional Description .......................................................1 Logic Block Diagram ..........................................................1 Contents ..............................................................................2 Device Operation ................................................................4 SRAM Read .................................................
CY14B104K, CY14B104M Pinouts Figure 1.
CY14B104K, CY14B104M Table 1. Pin Definitions (continued) Pin Name I/O Type INT Output Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain). Ground Ground for the Device. Must be connected to ground of the system. VSS VCC HSB VCAP Description Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10% Input/Output Hardware STORE Busy (HSB).
CY14B104K, CY14B104M Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 16 for the size of the VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull up should be placed on WE to hold it inactive during power up. This pull up is only effective if the WE signal is tristate during power up. Many MPUs tristate their controls on power up. Verify this when using the pull up.
CY14B104K, CY14B104M Table 2.
CY14B104K, CY14B104M Best Practices ■ Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. ■ The VCAP value specified in this data sheet includes a minimum and a maximum value size.
CY14B104K, CY14B104M Data Protection The CY14B104K/CY14B104M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B104K/CY14B104M is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active).
CY14B104K, CY14B104M must be set to ‘1’. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start. While system power is off, If the voltage on the backup supply (VRTCcap or VRTCbat) falls below their respective minimum level, the oscillator may fail.The CY14B104K has the ability to detect oscillator failure when system power is restored.
CY14B104K, CY14B104M New time out values are written by setting the watchdog write bit to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out value bits D5-D0 are enabled to modify the time out value. When WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified. A logical diagram of the watchdog timer is shown in Figure 3.
CY14B104K, CY14B104M with the value 0x00 on power up (except for the OSCF bit. See Stopping and Starting the Oscillator on page 8). Figure 4. RTC Recommended Component Configuration Recommended Values Y1 = 32.768 kHz (12.5 pF) C1 = 12 pF C2 = 69 pF Note The recommended values for C1 and C2 include board trace capacitance. C1 C2 Y1 Xout Xin Figure 5.
CY14B104K, CY14B104M Table 4.
CY14B104K, CY14B104M Table 5. Register Map Detail Register CY14B104K CY14B104M 0x7FFFF 0x3FFFF Description Time Keeping - Years D7 D6 D5 D4 D3 D2 10s Years D1 D0 Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
CY14B104K, CY14B104M Table 5. Register Map Detail (continued) Register CY14B104K CY14B104M 0x7FFF8 0x3FFF8 OSCEN Description Calibration/Control D7 D6 D5 OSCEN 0 Calibration Sign D4 D3 D2 D1 D0 Calibration Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage.
CY14B104K, CY14B104M Table 5. Register Map Detail (continued) Register CY14B104K CY14B104M 0x7FFF4 0x3FFF4 Description Alarm - Hours D7 D6 M 0 D5 D4 D3 10s Alarm Hours D2 D1 D0 Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M 0x7FFF3 Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value.
CY14B104K, CY14B104M Maximum Ratings Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Storage Temperature ................................. –65°C to +150°C Maximum Accumulated Storage Time Surface Mount Pb Soldering Temperature (3 Seconds) ......
CY14B104K, CY14B104M Data Retention and Endurance Parameter Description DATAR Data Retention NVC Nonvolatile STORE Operations Min Unit 20 Years 1,000 K Max Unit 7 pF 7 pF Capacitance In the following table, the capacitance parameters are listed. [13] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC (Typ) Thermal Resistance In the following table, the thermal resistance parameters are listed.
CY14B104K, CY14B104M RTC Characteristics Parameters Description VRTCbat RTC Battery Pin Voltage IBAK[14] RTC Backup Current Min Typ[11] 1.8 3.0 TA (Min) 25°C RTC Capacitor Pin Voltage tOCS RTC Oscillator Time to Start RBKCHG RTC Backup Capacitor Charge Current-Limiting Resistor TA (Min) 1.6 25°C 1.5 TA (Max) 1.4 3.0 1 350 Units 3.6 V 0.35 μA 0.5 μA 3.6 V 3.6 V μA 0.35 TA (Max) VRTCcap[15] Max 3.6 V 2 sec 850 Ω Notes 14. From either VRTCcap or VRTCbat. 15.
CY14B104K, CY14B104M AC Switching Characteristics Parameters Cypress Alt Parameters Parameters SRAM Read Cycle tACE tACS [16] tRC tRC tAA tAA [17] tDOE tOE [17] tOH tOHA tLZCE [13, 18] tLZ tHZCE [13, 18] tHZ [13, 18] tLZOE tOLZ tHZOE [13, 18] tOHZ tPU [13] tPA [13] tPD tPS tDBE tLZBE[13] [13] tHZBE SRAM Write Cycle tWC tWC tWP tPWE tSCE tCW tSD tDW tHD tDH tAW tAW tSA tAS tHA tWR [13, 18,19] tHZWE tWZ tLZWE [13, 18] tOW tBW - 25 ns Description Chip Enable Access Time Read Cycle Time Address Access Time O
CY14B104K, CY14B104M Figure 8. SRAM Read Cycle 2: CE and OE Controlled[3, 16, 20] Address Address Valid tRC tACE CE tHZCE tAA tLZCE tHZOE tDOE OE tHZBE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance ICC Output Data Valid tPU tPD Active Standby Figure 9. SRAM Write Cycle 1: WE Controlled[3, 19, 20, 21] tWC Address Address Valid tSCE tHA CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input Input Data Valid tHZWE Data Output tHD Previous Data tLZWE High Impedance Note 21.
CY14B104K, CY14B104M Switching Waveforms Figure 10. SRAM Write Cycle 2: CE Controlled[3, 19, 20, 21] tWC Address Valid Address tSA tSCE tHA CE tBW BHE, BLE tPWE WE tHD tSD Input Data Valid Data Input High Impedance Data Output Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[6, 19, 20, 21, 22] (Not applicable for RTC register writes) tWC Address Address Valid tSCE CE tSA tHA tBW BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output Note 22.
CY14B104K, CY14B104M AutoStore/Power Up RECALL Parameters tHRECALL [23] tSTORE [24] tDELAY [25] VSWITCH tVCCRISE[13] VHDIS[13] tLZHSB[13] tHHHD[13] CY14B104K/CY14B104M Min Max 20 8 25 2.65 150 1.9 5 500 Description Power Up RECALL Duration STORE Cycle Duration Time Allowed to Complete SRAM Write Cycle Low Voltage Trigger Level VCC Rise Time HSB Output Disable Voltage HSB To Output Active Time HSB High Active Time Unit ms ms ns V μs V μs ns Switching Waveforms Figure 12.
CY14B104K, CY14B104M Software Controlled STORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [28, 29] Parameters tRC tSA tCW tHA tRECALL tSS [30, 31] 25 ns Description Min 25 0 20 0 STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time 45 ns Max Min 45 0 30 0 200 100 Unit Max ns ns ns ns μs μs 200 100 Switching Waveforms Figure 13.
CY14B104K, CY14B104M Hardware STORE Cycle Parameters CY14B104K/CY14B104M Description Min tDHSB HSB To Output Active Time when write latch not set tPHSB Hardware STORE Pulse Width Max 25 Unit ns 15 ns Switching Waveforms Figure 15.
CY14B104K, CY14B104M Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations.
CY14B104K, CY14B104M Part Numbering Nomenclature CY14 B 104 K ZSP 25 X I T Option: T - Tape & Reel Blank - Std. Temperature: I - Industrial (–40 to 85°C) Pb-free Speed: 25 - 25 ns 45 - 45 ns Package: ZSP - 44 TSOP II ZSP - 54 TSOP II Data Bus: K - x8 + RTC M - x16 + RTC Density: 104 - 4 Mb Voltage: B - 3.
CY14B104K, CY14B104M Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) PIN 1 I.D. 10.262 (0.404) 10.058 (0.396) 1 11.938 (0.470) 11.735 (0.462) 22 ORE K X A SG EJECTOR PIN 23 44 BOTTOM VIEW TOP VIEW 0.800 BSC (0.0315) 0.400(0.016) 0.300 (0.012) BASE PLANE 18.517 (0.729) 18.313 (0.721) DIMENSION IN MM (INCH) MAX MIN. Document #: 001-07103 Rev. *O 0.10 (.004) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 10.262 (0.404) 10.058 (0.396) SEATING PLANE 0.210 (0.0083) 0.120 (0.
CY14B104K, CY14B104M Package Diagrams (continued) Figure 18. 54-Pin TSOP II (51-85160) 51-85160 ** Document #: 001-07103 Rev.
CY14B104K, CY14B104M Document History Page Document Title: CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Orig. of Submission Rev. ECN No.
CY14B104K, CY14B104M Document History Page (continued) Document Title: CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Orig. of Submission Rev. ECN No. Description of Change Change Date *F 1890926 vsutmp8/AESee ECN Added Footnote 1, 2 and 3. SA Updated Logic Block diagram Updated Pin definition Table Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8) package.
CY14B104K, CY14B104M Document History Page (continued) Document Title: CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Orig. of Submission Rev. ECN No.
CY14B104K, CY14B104M Document History Page (continued) Document Title: CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Orig. of Submission Rev. ECN No.
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