Specifications

CY14B104K, CY14B104M
Document #: 001-07103 Rev. *O Page 19 of 33
AC Switching Characteristics
Parameters
Description
25 ns 45 ns
Unit
Cypress
Parameters
Alt
Parameters
Min Max Min Max
SRAM Read Cycle
t
ACE
t
ACS
Chip Enable Access Time 25 45 ns
t
RC
[16]
t
RC
Read Cycle Time 25 45 ns
t
AA
[17]
t
AA
Address Access Time 25 45 ns
t
DOE
t
OE
Output Enable to Data Valid 12 20 ns
t
OHA
[17]
t
OH
Output Hold After Address Change 3 3 ns
t
LZCE
[13, 18]
t
LZ
Chip Enable to Output Active 3 3 ns
t
HZCE
[13, 18]
t
HZ
Chip Disable to Output Inactive 10 15 ns
t
LZOE
[13, 18]
t
OLZ
Output Enable to Output Active 0 0 ns
t
HZOE
[13, 18]
t
OHZ
Output Disable to Output Inactive 10 15 ns
t
PU
[13]
t
PA
Chip Enable to Power Active 0 0 ns
t
PD
[13]
t
PS
Chip Disable to Power Standby 25 45 ns
t
DBE
- Byte Enable to Data Valid 12 20 ns
t
LZBE
[13]
- Byte Enable to Output Active 0 0 ns
t
HZBE
[13]
- Byte Disable to Output Inactive 10 15 ns
SRAM Write Cycle
t
WC
t
WC
Write Cycle Time 25 45 ns
t
PWE
t
WP
Write Pulse Width 20 30 ns
t
SCE
t
CW
Chip Enable To End of Write 20 30 ns
t
SD
t
DW
Data Setup to End of Write 10 15 ns
t
HD
t
DH
Data Hold After End of Write 0 0 ns
t
AW
t
AW
Address Setup to End of Write 20 30 ns
t
SA
t
AS
Address Setup to Start of Write 0 0 ns
t
HA
t
WR
Address Hold After End of Write 0 0 ns
t
HZWE
[13, 18,19]
t
WZ
Write Enable to Output Disable 10 15 ns
t
LZWE
[13, 18]
t
OW
Output Active after End of Write 3 3 ns
t
BW
- Byte Enable to End of Write 20 30 ns
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled
[16, 17, 20]
Address
Data Output
Address Valid
Previous Data Valid
Output Data Valid
t
RC
t
AA
t
OHA
Notes
16. WE
must be HIGH during SRAM read cycles.
17. Device is continuously selected with CE
, OE and BHE / BLE LOW.
18. Measured ±200 mV from steady state output voltage.
19. If WE
is LOW when CE goes LOW, the outputs remain in the high impedance state.
20. HSB
must remain HIGH during read and write cycles.
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