Specifications

CY14B104K, CY14B104M
Document #: 001-07103 Rev. *O Page 24 of 33
Hardware STORE Cycle
Parameters Description
CY14B104K/CY14B104M
Unit
Min Max
t
DHSB
HSB To Output Active Time when write latch not set 25 ns
t
PHSB
Hardware STORE Pulse Width 15 ns
Switching Waveforms
Figure 15. Hardware STORE Cycle
[24]
Figure 16. Soft Sequence Processing
[30, 31]
t
PHSB
t
PHSB
t
DELAY
t
DHSB
t
DELAY
t
STORE
t
HHHD
t
LZHSB
Write latch set
Write latch not set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
HSB (IN)
HSB (OUT)
RWI
HSB pin is driven high to V
CC
only by Internal
SRAM is disabled as long as HSB (IN) is driven low
.
HSB driver is disabled
t
DHSB
100kOhm resistor,
Address #1 Address #6 Address #1 Address #6
Soft Sequence
Command
t
SS
t
SS
CE
Address
V
CC
t
SA
t
CW
Soft Sequence
Command
t
CW
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