Specifications

ManualsBrandsCypress ManualsComputer HardwareCY14B104M

PRELIMINARY

CY14B104K/CY14B104M

4 Mbit (512K x 8/256K x 16) nvSRAM with

Real-Time-Clock

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-07103 Rev. *I Revised June 20, 2008

Features

■ 15 ns, 20 ns, 25 ns, and 45 ns access times

■ Internally organized as 512K x 8 (CY14B104K) or 256K x 16

(CY14B104M)

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap

nonvolatile elements is initiated by

software, device pin, or AutoStore

on power down

■ RECALL to SRAM initiated by software or power up

■ High reliability

■ Infinite read, write, and recall cycles

■ 200,000 STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 3V +20%, –10% operation

■ Data integrity of Cypress nvSRAM combined with full featured

Real-Time-Clock

■ Watchdog timer

■ Clock alarm with programmable interrupts

■ Capacitor or battery backup for RTC

■ Commercial and industrial temperatures

■ 44/54-pin TSOP II package

■ Pb-free and RoHS compliance

Functional Description

The Cypress CY14B104K/CY14B104M combines a 4-Mbit

nonvolatile static RAM with a full featured real-time-clock in a

monolithic integrated circuit. The embedded nonvolatile

elements incorporate QuantumTrap technology producing the

world’s most reliable nonvolatile memory. The SRAM is read and

written an infinite number of times, while independent nonvolatile

data resides in the nonvolatile elements.

The real-time-clock function provides an accurate clock with leap

year tracking and a programmable, high accuracy oscillator. The

alarm function is programmable for one time alarms or periodic

seconds, minutes, hours, or days. There is also a programmable

watchdog timer for process control.

CAP

HSB

CY14B104K

RTCcap

RTCbat

INT

BHE

BLE

Logic Block Diagram

- A

Address

DQ0 - DQ7

CY14B104M

[1]

Note

1. Address A

- A

and DQ0 - DQ7 for x8 configuration, Address A

- A

and Data DQ0 - DQ15 for x16 configuration.

[+] Feedback

Summary of content (29 pages)

PAGE 1
PRELIMINARY CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real-Time-Clock Features ■ 15 ns, 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104K) or 256K x 16 (CY14B104M) ■ Hands off automatic STORE on power down with only a small capacitor ■ STORE to QuantumTrap® nonvolatile elements is initiated by software, device pin, or AutoStore® on power down ■ RECALL to SRAM initiated by software or power up ■ High reliability ■ Infinite read, write, and reca
PAGE 2
PRELIMINARY CY14B104K/CY14B104M Pinouts Figure 1.
PAGE 3
PRELIMINARY CY14B104K/CY14B104M Pin Definitions (continued) Pin Name IO Type INT Output Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain). VSS Ground Ground for the Device. Must be connected to ground of the system. VCC HSB VCAP Description Power Supply Power Supply Inputs to the Device. 3.
PAGE 4
PRELIMINARY CY14B104K/CY14B104M The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. Hardware STORE (HSB) Operation To initiate the software STORE cycle, the following read sequence must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5.
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PRELIMINARY CY14B104K/CY14B104M Table 1.
PAGE 6
PRELIMINARY CY14B104K/CY14B104M Data Protection The CY14B104K/CY14B104M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B104K/CY14B104M is in a write mode (both CE and WE LOW) at power up, after a RECALL, or after a STORE, the write is inhibited until a negative transition on CE or WE is detected.
PAGE 7
PRELIMINARY CY14B104K/CY14B104M If the voltage on the backup supply (VRTCcap or VRTCbat) falls below their respective minimum level, the oscillator may fail, leading to the oscillator failed condition which is detected when system power is restored. The value of OSCF must be reset to ‘0’ when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on.
PAGE 8
PRELIMINARY CY14B104K/CY14B104M . Figure 3. Watchdog Timer Block Diagram After an interrupt source is active, the pin driver determines the behavior of the output. It has two programmable settings. Pin driver control bits are located in the interrupt register. According to the programming selections, the pin is driven in the backup mode for an alarm interrupt. In addition, the pin is an active LOW (open drain) or an active HIGH (push pull) driver.
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PRELIMINARY CY14B104K/CY14B104M Figure 4. RTC Recommended Component Configuration Recommended Values Y1 = 32.768KHz RF = 10M Ohm C1 = 0 C2 = 56 pF Figure 5. Interrupt Block Diagram Legend WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low Document #: 001-07103 Rev.
PAGE 10
PRELIMINARY CY14B104K/CY14B104M Table 3.
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PRELIMINARY CY14B104K/CY14B104M Table 4. Register Map Detail Time Keeping - Years D7 D6 0x1FFFF D5 D4 D3 D2 10s Years D1 D0 Years Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. Time Keeping - Months 0x1FFFE D7 D6 D5 D4 0 0 0 10s Month D3 D2 D1 D0 Months Contains the BCD digits of the month.
PAGE 12
PRELIMINARY CY14B104K/CY14B104M Table 4. Register Map Detail (continued) WatchDog Timer 0x1FFF7 D7 D6 WDS WDW D5 D4 D3 D2 D1 D0 WDT WDS Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0. WDW Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT5–WDT0) so it cannot be written.
PAGE 13
PRELIMINARY CY14B104K/CY14B104M Table 4. Register Map Detail (continued) M Match. When this bit is set to 0, the seconds’ value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value. Time Keeping - Centuries 0x1FFF1 D7 D6 0 0 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 D1 D0 WDF AF PF OSCF 0 CAL W R 10s Centuries D1 D0 Centuries Flags 0x1FFF0 WDF Watchdog Timer Flag.
PAGE 14
PRELIMINARY CY14B104K/CY14B104M Maximum Ratings Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260°C Storage Temperature ................................. –65°C to +150°C Output Short Circuit Current[8] .....................................
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PRELIMINARY CY14B104K/CY14B104M Capacitance In the following table, the capacitance parameters are listed. [11] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0V Max Unit 7 pF 7 pF Thermal Resistance In the following table, the thermal resistance parameters are listed.
PAGE 16
PRELIMINARY CY14B104K/CY14B104M AC Switching Characteristics Parameters 15 ns Description Cypress Alt Parameters Parameters Min 20 ns Max Min 25 ns Max Min Max 45 ns Min Max Unit SRAM Read Cycle tACE tACS Chip Enable Access Time tRC [15] tRC Read Cycle Time [16] tAA 15 15 20 20 25 25 45 45 ns ns tAA Address Access Time 15 20 25 45 ns tDOE tOE Output Enable to Data Valid 10 10 12 20 ns tOHA tOH Output Hold After Address Change 3 3 3 3 ns tLZCE [17] tLZ Chi
PAGE 17
PRELIMINARY CY14B104K/CY14B104M Software Controlled STORE/RECALL Cycle In the following table, the software controlled STORE/RECALL cycle parameters are listed.
PAGE 18
PRELIMINARY CY14B104K/CY14B104M Switching Waveforms (continued) Figure 8. SRAM Read Cycle #2: CE Controlled[15, 26, 28] tRC ADDRESS tACE tLZCE CE tPD tHZCE OE tLZOE t HZOE tDOE BHE , BLE tLZBE DQ (DATA OUT) tHZCE tHZBE tDBE DATA VALID t PU ACTIVE STANDBY ICC Figure 9. SRAM Write Cycle #1: WE Controlled[18, 26, 27, 28] tWC ADDRESS tHA tSCE CE tAW tSA tPWE WE tBW BHE , BLE tSD DATA VALID DATA IN tHZWE DATA OUT tHD PREVIOUS DATA HIGH IMPEDANCE tLZWE Notes 27.
PAGE 19
PRELIMINARY CY14B104K/CY14B104M Switching Waveforms (continued) Figure 10. SRAM Write Cycle #2: CE Controlled[18, 26, 27, 28] tWC ADDRESS tSA tSCE CE tHA tAW tPWE WE tBW BHE , BLE tSD DATA IN tHD DATA VALID HIGH IMPEDANCE DATA OUT Figure 11. AutoStore/Power Up RECALL[29] No STORE occurs without atleast one SRAM write STORE occurs only if a SRAM write has happened VCC VSWITCH tVCCRISE AutoStore tSTORE tSTORE POWER-UP RECALL tHRECALL tHRECALL Read & Write Inhibited Note 29.
PAGE 20
PRELIMINARY CY14B104K/CY14B104M Switching Waveforms (continued) Figure 12. CE Controlled Software STORE/RECALL Cycle[22] ADDRESS # 1 ADDRESS # 1 CE CE OE OE tAS tAS tGLAX tGHAX DQ (DATA) DQ (DATA) Document #: 001-07103 Rev. *I ADDRESS # 6 ADDRESS # 6 tCW tCW DATA VALID DATA VALID a a a a ADDRESS ADDRESS tRC tRC a a a a a a a a a a a a a a a a tRC tRC a a a a a a a a Figure 13.
PAGE 21
PRELIMINARY CY14B104K/CY14B104M Switching Waveforms (continued) Figure 14. Hardware STORE Cycle[25] Figure 15. Soft Sequence Processing[23, 24] tSS Document #: 001-07103 Rev.
PAGE 22
PRELIMINARY CY14B104K/CY14B104M PART NUMBERING NOMENCLATURE CY 14 B 104 K - ZS P 15 X C T Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Pb-Free P - 54 Pin Blank - 44 Pin Speed: 15 - 15 ns 20 - 20 ns 25 - 25 ns 45 - 45 ns Package: ZS - TSOP II Data Bus: K - x8 + RTC M - x16 + RTC Density: 104 - 4 Mb Voltage: B - 3.0V NVSRAM 14 - AutoStore + Software Store + Hardware Store Cypress Document #: 001-07103 Rev.
PAGE 23
PRELIMINARY CY14B104K/CY14B104M Ordering Information Speed (ns) 15 20 25 Ordering Code Package Diagram Package Type Operating Range CY14B104K-ZS15XCT 51-85087 44-pin TSOPII Commercial CY14B104K-ZS15XIT 51-85087 44-pin TSOPII Industrial CY14B104K-ZS15XI 51-85087 44-pin TSOPII CY14B104M-ZS15XCT 51-85087 44-pin TSOPII Commercial CY14B104M-ZS15XIT 51-85087 44-pin TSOPII Industrial CY14B104M-ZS15XI 51-85087 44-pin TSOPII CY14B104K-ZSP15XCT 51-85160 54-pin TSOPII Commercial CY14B
PAGE 24
PRELIMINARY CY14B104K/CY14B104M Ordering Information (continued) Speed (ns) 45 Ordering Code Package Diagram Package Type Operating Range CY14B104K-ZS45XCT 51-85087 44-pin TSOPII Commercial CY14B104K-ZS45XIT 51-85087 44-pin TSOPII Industrial CY14B104K-ZS45XI 51-85187 44-pin TSOPII CY14B104M-ZS45XCT 51-85087 44-pin TSOPII Commercial CY14B104M-ZS45XIT 51-85087 44-pin TSOPII Industrial CY14B104M-ZS45XI 51-85087 44-pin TSOPII CY14B104K-ZSP45XCT 51-85160 54-pin TSOPII Commercial C
PAGE 25
PRELIMINARY CY14B104K/CY14B104M Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 1 23 10.262 (0.404) 10.058 (0.396) 11.938 (0.470) 11.735 (0.462) 22 EJECTOR PIN 44 TOP VIEW 0.800 BSC (0.0315) OR E K X A SG BOTTOM VIEW 0.400(0.016) 0.300 (0.012) 10.262 (0.404) 10.058 (0.396) BASE PLANE 0.210 (0.0083) 0.120 (0.0047) 0°-5° 0.10 (.004) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 18.517 (0.729) 18.313 (0.721) SEATING PLANE 0.
PAGE 26
PRELIMINARY CY14B104K/CY14B104M Package Diagrams (continued) Figure 17. 54-Pin TSOP II (51-85160) 51-85160-** Document #: 001-07103 Rev.
PAGE 27
PRELIMINARY CY14B104K/CY14B104M Document History Page Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real-Time-Clock Document Number: 001-07103 Orig. of Rev. ECN No.
PAGE 28
PRELIMINARY CY14B104K/CY14B104M Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real-Time-Clock Document Number: 001-07103 Orig. of Rev. ECN No. Submission Description of Change Date Change *F 1890926 See ECN vsutmp8/A Added Footnote 1, 2 and 3. ESA Updated Logic Block diagram Updated Pin definition Table Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8) package.
PAGE 29
PRELIMINARY CY14B104K/CY14B104M Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real-Time-Clock Document Number: 001-07103 Orig. of Rev. ECN No.