Specifications

PRELIMINARY

CY14B104K/CY14B104M

Document #: 001-07103 Rev. *I Page 13 of 29

M Match. When this bit is set to 0, the seconds’ value is used in the alarm match. Setting this bit to 1 causes the match

circuit to ignore the seconds value.

0x1FFF1

Time Keeping - Centuries

D7 D6 D5 D4 D3 D2 D1 D0

0 0 10s Centuries Centuries

0x1FFF0

Flags

D7 D6 D5 D4 D3 D2 D1 D0

WDF AF PF OSCF 0 CAL W R

WDF Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset

by the user. It is cleared to 0 when the Flags/Control register is read.

AF Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with

the match bits = 0. It is cleared when the Flags/Control register is read.

PF Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold V

SWITCH

. It is cleared to

0 when the Flags/Control register is read.

OSCF Oscillator Fail Flag. Set to 1 on power up only if the oscillator is not running in the first 5 ms of power on operation.

This indicates that time counts are no longer valid. The user must reset this bit to 0 to clear this condition. The chip

does not clear this flag. This bit survives power cycles.

CAL Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes

normal operation. This bit defaults to 0 (disabled) on power up.

W Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then write them with

updated values. Setting the W bit to 0 transfers the contents of the time registers to the timekeeping counters.

R Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a holding

from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 before reading again.

Table 4. Register Map Detail (continued)

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