Specifications
PRELIMINARY
CY14B104K/CY14B104M
Document #: 001-07103 Rev. *I Page 16 of 29
AC Switching Characteristics
Parameters
Description
15 ns 20 ns 25 ns 45 ns
Unit
Cypress
Parameters
Alt
Parameters
Min Max Min Max Min Max Min Max
SRAM Read Cycle
t
ACE
t
ACS
Chip Enable Access Time 15 20 25 45 ns
t
RC
[15]
t
RC
Read Cycle Time 15 20 25 45 ns
t
AA
[16]
t
AA
Address Access Time 15 20 25 45 ns
t
DOE
t
OE
Output Enable to Data Valid 10 10 12 20 ns
t
OHA
t
OH
Output Hold After Address Change 3 3 3 3 ns
t
LZCE
[17]
t
LZ
Chip Enable to Output Active 3 3 3 3 ns
t
HZCE
[17]
t
HZ
Chip Disable to Output Inactive 7 8 10 15 ns
t
LZOE
[17]
t
OLZ
Output Enable to Output Active 0 0 0 0 ns
t
HZOE
[17]
t
OHZ
Output Disable to Output Inactive 7 8 10 15 ns
t
PU
[11]
t
PA
Chip Enable to Power Active 0 0 0 0 ns
t
PD
[11]
t
PS
Chip Disable to Power Standby 15 20 25 45 ns
t
DBE
- Byte Enable to Data Valid 10 10 12 20 ns
t
LZBE
- Byte Enable to Output Active 0 0 0 0 ns
t
HZBE
- Byte Disable to Output Inactive 7 8 10 15 ns
SRAM Write Cycle
t
WC
t
WC
Write Cycle Time 15 20 25 45 ns
t
PWE
t
WP
Write Pulse Width 10152030ns
t
SCE
t
CW
Chip Enable To End of Write 15 15 20 30 ns
t
SD
t
DW
Data Setup to End of Write 5 8 10 15 ns
t
HD
t
DH
Data Hold After End of Write 0 0 0 0 ns
t
AW
t
AW
Address Setup to End of Write 10 15 20 30 ns
t
SA
t
AS
Address Setup to Start of Write 0 0 0 0 ns
t
HA
t
WR
Address Hold After End of Write 0 0 0 0 ns
t
HZWE
[17,18]
t
WZ
Write Enable to Output Disable 7 8 10 15 ns
t
LZWE
[17]
t
OW
Output Active after End of Write 3 3 3 3 ns
t
BW
- Byte Enable to End of Write 15 15 20 30 ns
AutoStore/Power Up RECALL
Parameters Description
CY14B104K/CY14B104M
Unit
Min Max
t
HRECALL
[19]
Power Up RECALL Duration 20 ms
t
STORE
[20]
STORE Cycle Duration 15 ms
V
SWITCH
Low Voltage Trigger Level 2.65 V
t
VCCRISE
VCC Rise Time 150 μs
Notes
15. WE
must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE
and OE both LOW.
17. Measured ±200 mV from steady state output voltage.
18. If WE
is low when CE goes low, the outputs remain in the high impedance state.
19. t
HRECALL
starts from the time V
CC
rises above V
SWITCH
.
20. If an SRAM write has not taken place since the last nonvolatile cycle, no STORE takes place.
[+] Feedback