Specifications

PRELIMINARY
CY14B104K/CY14B104M
Document #: 001-07103 Rev. *I Page 17 of 29
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.
[21, 22]
Parameters Description
15 ns 20 ns 25 ns 45 ns
Unit
Min Max Min Max Min Max Min Max
t
RC
STORE/RECALL Initiation Cycle Time 15 20 25 45 ns
t
AS
Address Setup Time 0 0 0 0 ns
t
CW
Clock Pulse Width 12152030 ns
t
GHAX
Address Hold Time 1 1 1 1 ns
t
RECALL
RECALL Duration 200 200 200 200 μs
t
SS
[23, 24]
Soft Sequence Processing Time 70 70 70 70 μs
Hardware STORE Cycle
Parameters Description
CY14B104K/CY14B104M
Unit
Min Max
t
DELAY
[25]
Time Allowed to Complete SRAM Cycle 1 70 μs
t
HLHX
Hardware STORE Pulse Width 15 ns
Switching Waveforms
Figure 7. SRAM Read Cycle #1: Address Controlled
[15, 16, 26]
t
RC
t
AA
t
OHA
ADDRESS
DQ (DATA OUT)
DATA VALID
Notes
21. The software sequence is clocked with CE
controlled or OE controlled reads.
22. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE
must be HIGH during all six consecutive cycles.
23. This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.
24. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command.
25. On a hardware STORE initiation, SRAM operation continues to be enabled for time t
DELAY
to allow read and write cycles to complete.
26. HSB must remain HIGH during read and write cycles.
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