Specifications

PRELIMINARY
CY14B104K/CY14B104M
Document #: 001-07103 Rev. *I Page 18 of 29
Figure 8. SRAM Read Cycle #2: CE
Controlled
[15, 26, 28]
Figure 9. SRAM Write Cycle #1: WE
Controlled
[18, 26, 27, 28]
Switching Waveforms (continued)
ADDRESS
t
RC
CE
t
ACE
t
LZCE
t
PD
t
HZCE
OE
t
DOE
t
LZOE
DATA VALID
ACTIVE
STANDBY
t
PU
DQ (DATA OUT)
ICC
t
LZBE
t
DBE
t
HZBE
HZOE
t
t
HZCE
BHE , BLE
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
BHE , BLE
t
BW
Notes
27. CE
or WE must be > VIH during address transitions.
28. BHE
and BLE are applicable for x16 configuration only.
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