Specifications

PRELIMINARY
CY14B104K/CY14B104M
Document #: 001-07103 Rev. *I Page 19 of 29
Figure 10. SRAM Write Cycle #2: CE
Controlled
[18, 26, 27, 28]
Figure 11. AutoStore/Power Up RECALL
[29]
Note
29. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
Switching Waveforms (continued)
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
BHE , BLE
t
BW
V
CC
V
SWITCH
t
STORE
t
STORE
t
HRECALL
t
HRECALL
AutoStore
POWER-UP RECALL
Read & Write Inhibited
STORE occurs only
if a SRAM write
has happened
No STORE occurs
without atleast one
SRAM write
t
VCCRISE
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