Specifications
PRELIMINARY
CY14B104K/CY14B104M
Document #: 001-07103 Rev. *I Page 2 of 29
Pinouts
Figure 1. Pin Diagram - 44/54 TSOP II
Pin Definitions
Pin Name IO Type Description
A
0
– A
18
Input Address Inputs Used to Select one of the 524, 288 bytes of the nvSRAM for x8 Configuration.
A
0
– A
17
Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x16 Configuration.
DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
NC No Connect No Connects. This pin is not connected to the die.
WE
Input Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE
.
CE
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE
HIGH causes the IO pins to tri-state.
BHE
Input Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
X
1
Output Crystal Connection. Drives crystal on start up.
X
2
Input Crystal Connection. For 32.768 kHz crystal.
V
RTCcap
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if V
RTCbat
is used.
V
RTCbat
Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if V
RTCcap
is used.
NC
A
8
X2
X1
V
SS
DQ6
DQ5
DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
A
17
A
18
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
A
10
V
RTCbat
WE
DQ7
HSB
INT
V
SS
V
CC
V
CAP
V
RTCcap
(x8)
A
17
DQ7
DQ6
DQ5
DQ4
V
CC
DQ3
DQ2
DQ1
DQ0
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CAP
WE
A
8
A
10
A
11
A
12
A
13
A
14
A
15
A
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
Top View
(not to scale)
OE
CE
V
CC
INT
V
SS
NC
A
9
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
(x16)
V
RTCcap
V
RTCbat
X2
X1
[2]
[2]
[3]
[3]
Notes
2. Address expansion for 8 Mbit. NC pin not connected to die.
3. Address expansion for 16 Mbit. NC pin not connected to die.
[+] Feedback