nvSRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY14B104N

CY14B104L, CY14B104N

4 Mbit (512K x 8/256K x 16) nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-07102 Rev. *L Revised December 19, 2008

Features

■ 20 ns, 25 ns, and 45 ns Access Times

■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16

(CY14B104N)

■ Hands off Automatic STORE on power down with only a small

Capacitor

■ STORE to QuantumTrap

nonvolatile elements initiated by

software, device pin, or AutoStore

on power down

■ RECALL to SRAM initiated by software or power up

■ Infinite Read, Write, and Recall Cycles

■ 200,000 STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 3V +20% to –10% operation

■ Commercial and Industrial Temperatures

■ 48-ball FBGA and 44/54-pin TSOP II packages

■ Pb-free and RoHS compliance

Functional Description

The Cypress CY14B104L/CY14B104N is a fast static RAM, with

a nonvolatile element in each memory cell. The memory is

organized as 512K bytes of 8 bits each or 256K words of 16 bits

each. The embedded nonvolatile elements incorporate

QuantumTrap technology, producing the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while independent nonvolatile data resides in the highly

reliable QuantumTrap cell. Data transfers from the SRAM to the

nonvolatile elements (the STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM (the RECALL operation) from the nonvolatile memory.

Both the STORE and RECALL operations are also available

under software control.

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Logic Block Diagram

[1, 2, 3]

Notes

1. Address A

- A

for x8 configuration and Address A

- A

for x16 configuration.

2. Data DQ

- DQ

for x8 configuration and Data DQ

- DQ

for x16 configuration.

3. BHE

and BLE are applicable for x16 configuration only.

[+] Feedback

Summary of content (25 pages)

PAGE 1
CY14B104L, CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Features Functional Description ■ 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off Automatic STORE on power down with only a small Capacitor ■ STORE to QuantumTrap® nonvolatile elements initiated by software, device pin, or AutoStore® on power down ■ RECALL to SRAM initiated by software or power up ■ Infinite Read, Write, and Recall Cycles ■ 200,000 STORE cycles to
PAGE 2
CY14B104L, CY14B104N Pinouts Figure 1.
PAGE 3
CY14B104L, CY14B104N Pinouts (continued) Figure 3.
PAGE 4
CY14B104L, CY14B104N The CY14B104L/CY14B104N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel.
PAGE 5
CY14B104L, CY14B104N Hardware RECALL (Power Up) The software sequence may be clocked with CE controlled reads or OE controlled reads. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB will be driven LOW. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.
PAGE 6
CY14B104L, CY14B104N Table 1.
PAGE 7
CY14B104L, CY14B104N Maximum Ratings Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Storage Temperature ................................. –65°C to +150°C Surface Mount Pb Soldering Temperature (3 Seconds) .......................................
PAGE 8
CY14B104L, CY14B104N Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 20 Years NVC Nonvolatile STORE Operations 200 K Capacitance In the following table, the capacitance parameters are listed.[13] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max Unit 7 pF 7 pF TA = 25°C, f = 1 MHz, VCC = 0 to 3.0V Thermal Resistance In the following table, the thermal resistance parameters are listed.
PAGE 9
CY14B104L, CY14B104N AC Switching Characteristics Parameters Cypress Parameters 20 ns Description Alt Parameters Min 25 ns Max Min 45 ns Max Min Max Unit SRAM Read Cycle tACE tACS Chip Enable Access Time tRC[14] tRC Read Cycle Time tAA[15] tAA Address Access Time 20 25 45 ns tDOE tOE Output Enable to Data Valid 10 12 20 ns tOHA[15] tOH Output Hold After Address Change 3 3 3 ns tLZCE[16] tLZ Chip Enable to Output Active 3 3 3 ns tHZCE[16] tLZOE[16] tHZOE[16] tPU
PAGE 10
CY14B104L, CY14B104N Figure 7. SRAM Read Cycle #2: CE and OE Controlled[3, 14, 18] $GGUHVV $GGUHVV 9DOLG W5& W+=&( W$&( &( W$$ W/=&( W+=2( W'2( 2( W+=%( W/=2( W'%( %+( %/( W/=%( 'DWD 2XWSXW +LJK ,PSHGDQFH 2XWSXW 'DWD 9DOLG W38 ,&& W3' $FWLYH 6WDQGE\ Figure 8. SRAM Write Cycle #1: WE Controlled[3, 17, 18, 19] W:& $GGUHVV $GGUHVV 9DOLG W6&( W+$ &( W%: %+( %/( W$: W3:( :( W6$ W6' 'DWD ,QSXW ,QSXW 'DWD 9DOLG W+=:( 'DWD 2XWSXW W+' 3UHYLRXV 'DWD W/=:( +LJK ,PSHGDQFH Notes 19.
PAGE 11
CY14B104L, CY14B104N Figure 9. SRAM Write Cycle #2: CE Controlled[3, 17, 18, 19] tWC Address Valid Address tSA tSCE tHA CE tBW BHE, BLE tPWE WE tHD tSD Input Data Valid Data Input High Impedance Data Output Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[3, 17, 18, 19] W:& $GGUHVV $GGUHVV 9DOLG W6&( &( W6$ W+$ W%: %+( %/( W$: W3:( :( W6' 'DWD ,QSXW W+' ,QSXW 'DWD 9DOLG +LJK ,PSHGDQFH 'DWD 2XWSXW Document #: 001-07102 Rev.
PAGE 12
CY14B104L, CY14B104N AutoStore/Power Up RECALL Parameters tHRECALL [20] tSTORE [21] tDELAY [22] VSWITCH tVCCRISE VHDIS[13] tHHHD tPURHH tLZHSB CY14B104L/CY14B104N Min Max 20 8 1 70 2.65 150 1.
PAGE 13
CY14B104L, CY14B104N Software Controlled STORE/RECALL Cycle In the following table, the software controlled STORE/RECALL cycle parameters are listed.[25, 26] Parameters tRC tSA tCW tHA tRECALL tSS [27, 28] 20 ns Min Max 20 0 15 0 200 100 Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time 25 ns Min Max 25 0 20 0 200 100 45 ns Min Max 45 0 30 0 200 100 Unit ns ns ns ns μs μs Switching Waveforms Figure 12.
PAGE 14
CY14B104L, CY14B104N Hardware STORE Cycle Parameters CY14B104L/CY14B104N Description tPHSB Hardware STORE Pulse Width tHLBL Hardware STORE LOW to STORE Busy Switching Waveforms Min Max 15 Unit ns 500 ns Figure 14. Hardware STORE Cycle[21] :ULWH ODWFK VHW W3+6% +6% ,1 W6725( W+++' W+/%/ +6% 287 W'(/$< W/=+6% '4 'DWD 2XW :ULWH ODWFK QRW VHW W3+6% +6% ,1 W+/%/ W+++' +6% 287 W'(/$< W/=+6% '4 'DWD 2XW Figure 15.
PAGE 15
CY14B104L, CY14B104N Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations.
PAGE 16
CY14B104L, CY14B104N Ordering Information Speed (ns) 20 25 Ordering Code Package Diagram Package Type Operating Range CY14B104L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B104L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B104L-ZS20XI 51-85087 44-pin TSOP II CY14B104L-BA20XCT 51-85128 48-ball FBGA Commercial CY14B104L-BA20XIT 51-85128 48-ball FBGA Industrial CY14B104L-BA20XI 51-85128 48-ball FBGA CY14B104L-ZSP20XCT 51-85160 54-pin TSOP II Commercial CY14B104L-ZSP20XIT
PAGE 17
CY14B104L, CY14B104N Ordering Information (continued) Speed (ns) 45 Ordering Code Package Diagram Package Type Operating Range CY14B104L-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B104L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B104L-ZS45XI 51-85087 44-pin TSOP II CY14B104L-BA45XCT 51-85128 48-ball FBGA Commercial Industrial CY14B104L-BA45XIT 51-85128 48-ball FBGA CY14B104L-BA45XI 51-85128 48-ball FBGA CY14B104L-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14B104L-ZS
PAGE 18
CY14B104L, CY14B104N Part Numbering Nomenclature CY 14 B 104 L - ZS P 20 X C T Option: T - Tape & Reel Blank - Std. Pb-Free P - 54 Pin Blank - 44 Pin Package: BA - 48 FBGA ZS - TSOP II Voltage: B - 3.0V Temperature: C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns Data Bus: L - x8 N - x16 Density: 104 - 4 Mb NVSRAM 14 - Auto Store + Software Store + Hardware Store Cypress Document #: 001-07102 Rev.
PAGE 19
CY14B104L, CY14B104N Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 1 23 10.262 (0.404) 10.058 (0.396) 11.938 (0.470) 11.735 (0.462) 22 EJECTOR PIN 44 TOP VIEW 0.800 BSC (0.0315) OR E K X A SG BOTTOM VIEW 0.400(0.016) 0.300 (0.012) 10.262 (0.404) 10.058 (0.396) BASE PLANE 0.210 (0.0083) 0.120 (0.0047) 0°-5° 0.10 (.004) Document #: 001-07102 Rev. *L 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 18.517 (0.729) 18.313 (0.
PAGE 20
CY14B104L, CY14B104N Package Diagrams (continued) Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 10.00±0.10 10.00±0.10 1 F G H H 1.875 A A B 0.75 6.00±0.10 0.53±0.05 B 0.15 C 0.21±0.05 0.25 C 3.75 6.00±0.10 0.15(4X) Document #: 001-07102 Rev. *L 1.20 MAX 0.
PAGE 21
CY14B104L, CY14B104N Package Diagrams (continued) Figure 18. 54-Pin TSOP II (51-85160) 51-85160-** Document #: 001-07102 Rev.
PAGE 22
CY14B104L, CY14B104N Document History Page Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Rev. ECN No. Submission Date Orig. of Change ** 431039 See ECN TUP New Data Sheet *A 489096 See ECN TUP Removed 48 SSOP Package Added 48 FBGA and 54 TSOPII Packages Updated Part Numbering Nomenclature and Ordering Information Added Soft Sequence Processing Time Waveform *B 499597 See ECN PCI Removed 35 ns speed bin Added 55 ns speed bin.
PAGE 23
CY14B104L, CY14B104N Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Rev. ECN No. Submission Date Orig. of Change Description of Change *F 1889928 See ECN vsutmp8/AESA Added Footnotes 1, 2 and 3. Updated logic block diagram Added 48-FBGA (X8) Pin Diagram Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8). Updated pin definitions table.
PAGE 24
CY14B104L, CY14B104N Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Rev. ECN No. Submission Date Orig.
PAGE 25
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