Specifications

ManualsBrandsCypress ManualsComputer HardwareCY14B108K

CY14B108K

CY14B108M

8-Mbit (1024 K × 8/512 K × 16) nvSRAM

with Real Time Clock

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-47378 Rev. *K Revised September 12, 2014

8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock

Features

■ 25 ns and 45 ns access times

■ Internally organized as 1024 K × 8 (CY14B108K) or 512 K × 16

(CY14B108M)

■ Hands off automatic STORE on power-down with only a small

capacitor

■ STORE to QuantumTrap nonvolatile elements is initiated by

software, device pin, or AutoStore on power-down

■ RECALL to SRAM initiated by software or power-up

■ High reliability

■ Infinite Read, Write, and RECALL cycles

■ 1 million STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 3 V +20%, –10% operation

■ Data integrity of Cypress nonvolatile static RAM (nvSRAM)

combined with full-featured real time clock (RTC)

■ Watchdog timer

■ Clock alarm with programmable interrupts

■ Capacitor or battery backup for RTC

■ Industrial temperature

■ 44 and 54-pin thin small outline package (TSOP) Type II

■ Pb-free and restriction of hazardous substances (RoHS)

compliant

Functional Description

The Cypress CY14B108K/CY14B108M combines a 8-Mbit

nonvolatile static RAM (nvSRAM) with a full featured RTC in a

monolithic integrated circuit. The embedded nonvolatile

elements incorporate QuantumTrap technology producing the

world’s most reliable nonvolatile memory. The SRAM is read and

written infinite number of times, while independent nonvolatile

data resides in the nonvolatile elements.

The RTC function provides an accurate clock with leap year

tracking and a programmable, high accuracy oscillator. The

alarm function is programmable for periodic minutes, hours,

days, or months alarms. There is also a programmable watchdog

timer for process control.

Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 33. Details include errata trigger conditions, scope of impact,

available workarounds, and silicon revision applicability.

Summary of content (36 pages)

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CY14B108K CY14B108M 8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock 8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock Features ■ 25 ns and 45 ns access times ■ Internally organized as 1024 K × 8 (CY14B108K) or 512 K × 16 (CY14B108M) ■ Hands off automatic STORE on power-down with only a small capacitor ■ STORE to QuantumTrap nonvolatile elements is initiated by software, device pin, or AutoStore on power-down ■ RECALL to SRAM initiated by software or power-up ■ High reliabili
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CY14B108K CY14B108M Logic Block Diagram [1, 2, 3] Quatrum Trap 2048 X 2048 X 2 A0 A1 A2 R O W A3 A4 A5 A6 A7 A8 A17 A18 D E C O D E R STORE VCC VCAP POWER CONTROL VRTCbat VRTCcap RECALL STATIC RAM ARRAY 2048 X 2048 X 2 STORE/RECALL CONTROL SOFTWARE DETECT HSB A14 - A2 A 19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 RTC I N P U T B U F F E R S Xout Xin INT COLUMN I/O MUX A19- A 0 OE COLUMN DEC WE DQ12 DQ13 CE DQ14 DQ15 A9 A10 A11 A12 A13 A14 A15 A16 BLE BHE Notes 1.
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CY14B108K CY14B108M Contents Pinouts .............................................................................. 4 Pin Definitions .................................................................. 5 Device Operation .............................................................. 6 SRAM Read ................................................................ 6 SRAM Write ................................................................. 6 AutoStore Operation ...................................................
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CY14B108K CY14B108M Pinouts Figure 1.
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CY14B108K CY14B108M Pin Definitions Pin Name A0–A19 A0–A18 DQ0–DQ7 DQ0–DQ15 NC WE CE OE I/O Type Input Input/Output No connect Input Input Input Input Input Output Input [5] Power supply VRTCcap VRTCbat[5] Power supply [5] Output INT BHE BLE Xout[5] Xin[5] VSS VCC HSB VCAP Ground Power supply Input/Output Power supply Description Address inputs. Used to select one of the 1,048,576 bytes of the nvSRAM for × 8 configuration. Address inputs.
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CY14B108K CY14B108M The CY14B108K/CY14B108M nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel.
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CY14B108K CY14B108M the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B108K/CY14B108M. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source.
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CY14B108K CY14B108M Table 1.
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CY14B108K CY14B108M Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5.
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CY14B108K CY14B108M Real Time Clock Operation nvTime Operation The CY14B108K/CY14B108M offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation.
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CY14B108K CY14B108M within the first 5 ms, the OSCF bit is set to ‘1’. The system must check for this condition and then write ‘0’ to clear the flag. Note that in addition to setting the OSCF flag bit, the time registers are reset to the ‘Base Time’, which is the value last written to the timekeeping registers. The control or calibration registers and the OSCEN bit are not affected by the ‘oscillator failed’ condition.
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CY14B108K CY14B108M flag and the hardware interrupt are both cleared when user reads the flags registers. Figure 3. Watchdog Timer Block Diagram Clock Divider Oscillator 32,768 KHz 32 Hz Zero Compare WDF Load Register WDS Q D WDW Q write to Watchdog Register Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. Note CY14B108K generates valid interrupts only after the Power-up RECALL sequence is completed.
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CY14B108K CY14B108M Figure 4. Interrupt Block Diagram WDF Watchdog Timer WIE P/L VCC PF Power Monitor Pin Driver PFE INT VINT H/L WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low VSS AF Clock Alarm AIE RTC External Components The RTC requires connecting an external 32.768 kHz crystal and C1, C2 load capacitance as shown in the Figure 5.
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CY14B108K CY14B108M PCB Design Considerations for RTC RTC crystal oscillator is a low current circuit with high impedance nodes on their crystal pins. Due to lower timekeeping current of RTC, the crystal connections are very sensitive to noise on the board. Hence it is necessary to isolate the RTC circuit from other signals on the board. It is also critical to minimize the stray capacitance on the PCB.
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CY14B108K CY14B108M Table 3.
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CY14B108K CY14B108M Table 4. Register Map Detail Register CY14B108K CY14B108M 0xFFFFF 0x7FFFF Description Time Keeping - Years D7 D6 D5 D4 D3 D2 10s years D1 D0 Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
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CY14B108K CY14B108M Table 4. Register Map Detail (continued) Register CY14B108K CY14B108M 0xFFFF8 0x7FFF8 OSCEN Calibration Sign Calibration 0xFFFF7 0x7FFF7 Description Calibration/Control D7 D6 D5 OSCEN 0 Calibration sign D4 D3 D2 D1 D0 Calibration Oscillator enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage.
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CY14B108K CY14B108M Table 4. Register Map Detail (continued) Register CY14B108K CY14B108M 0xFFFF4 0x7FFF4 Description Alarm - Hours D7 D6 M 0 D5 D4 D3 10s alarm hours D2 D1 D0 Alarm hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M 0xFFFF3 Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the hours value.
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CY14B108K CY14B108M Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25°C) .................................................. 1.0 W Maximum accumulated storage time Surface mount Pb soldering temperature (3 Seconds) .......
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CY14B108K CY14B108M DC Electrical Characteristics (continued) Over the Operating Range Parameter VCAP[19] VVCAP[20, 21] Description Storage capacitor Test Conditions Min Typ[17] Max Unit Between VCAP pin and VSS, 5 V rated 122 150 360 F – – VCC V Maximum voltage driven on VCAP VCC = Max pin by the device Data Retention and Endurance Over the Operating Range Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 20 Years 1,000 K Max Unit 14 pF 1
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CY14B108K CY14B108M AC Test Loads Figure 7. AC Test Loads 577  577  3.0 V 3.0 V R1 R1 OUTPUT OUTPUT R2 789  30 pF R2 789  5 pF AC Test Conditions Input pulse levels ...................................................0 V to 3 V Input rise and fall times (10%–90%) ........................... < 3 ns Input and output timing reference levels ....................... 1.
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CY14B108K CY14B108M AC Switching Characteristics Over the Operating Range Parameters [25] Cypress Alt Parameter Parameter SRAM Read Cycle tACE tACS tRC tRC [26] tAA [27] tAA tOE tDOE [27] tOH tOHA tLZCE [28, 29] tLZ tHZ tHZCE [28, 29] tOLZ tLZOE [28, 29] tHZOE [28, 29] tOHZ tPA tPU [28] tPS tPD [28] tDBE [28] tLZBE tHZBE[28] SRAM Write Cycle tWC tWC tWP tPWE tSCE tCW tDW tSD tDH tHD tAW tAW tAS tSA tWR tHA tHZWE [28, 29, 30] tWZ tOW tLZWE [28, 29] tBW 25 ns Description 45 ns Unit Min Max Min Max Chi
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CY14B108K CY14B108M Switching Waveforms (continued) Figure 9. SRAM Read Cycle 2 (CE and OE Controlled) [32, 33, 34] Address Address Valid tRC tHZCE tACE CE tAA tLZCE tHZOE tDOE OE tHZBE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance Output Data Valid tPU ICC tPD Active Standby Figure 10.
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CY14B108K CY14B108M Switching Waveforms (continued) Figure 11. SRAM Write Cycle 2 (CE Controlled) [37, 38, 39, 40] tWC Address Valid Address tSA tSCE tHA CE tBW BHE, BLE tPWE WE tHD tSD Input Data Valid Data Input High Impedance Data Output Figure 12.
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CY14B108K CY14B108M AutoStore/Power-Up RECALL Over the Operating Range Parameter CY14B108K/CY14B108M Description Min Max Unit tHRECALL [43] Power-Up RECALL duration – 20 ms tSTORE [44] STORE cycle duration – 8 ms tDELAY [45] VSWITCH tVCCRISE [46] Time allowed to complete SRAM write cycle – 25 ns Low voltage trigger level – 2.65 V 150 – s – 1.
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CY14B108K CY14B108M Software Controlled STORE and RECALL Cycle Over the Operating Range Parameter [49, 50] tRC tSA tCW tHA tRECALL tSS [51, 52] 25 ns Description Min 25 0 20 0 – – STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration Soft sequence processing time 45 ns Max – – – – 200 100 Min 45 0 30 0 – – Max – – – – 200 100 Unit ns ns ns ns s s Switching Waveforms Figure 14.
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CY14B108K CY14B108M Hardware STORE Cycle Over the Operating Range Parameter CY14B108K/CY14B108M Description Min Max Unit tDHSB HSB to output active time when write latch not set – 25 ns tPHSB Hardware STORE pulse width 15 – ns Switching Waveforms Figure 16.
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CY14B108K CY14B108M Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. Table 5. Truth Table for × 8 Configuration CE Inputs and Outputs[57] WE OE Mode Power H X X High Z Deselect/Power-down Standby L H L Data out (DQ0–DQ7); Read Active L H H High Z Output disabled Active L L X Data in (DQ0–DQ7); Write Active Table 6.
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CY14B108K CY14B108M Ordering Information Speed (ns) 25 45 Ordering Code CY14B108K-ZS25XIT Package Diagram 51-85087 Package Type 44-pin TSOPII CY14B108K-ZS25XI 51-85087 44-pin TSOPII CY14B108M-ZSP25XIT 51-85160 54-pin TSOPII CY14B108M-ZSP25XI 51-85160 54-pin TSOPII CY14B108K-ZS45XIT 51-85087 44-pin TSOPII CY14B108K-ZS45XI 51-85087 44-pin TSOPII CY14B108M-ZSP45XIT 51-85160 54-pin TSOPII CY14B108M-ZSP45XI 51-85160 54-pin TSOPII Operating Range Industrial All the above parts are Pb-f
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CY14B108K CY14B108M Package Diagrams Figure 18. 44-pin TSOP II Package Outline, 51-85087 51-85087 *E Document Number: 001-47378 Rev.
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CY14B108K CY14B108M Package Diagrams (continued) Figure 19. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Package Outline, 51-85160 51-85160 *E Document Number: 001-47378 Rev.
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CY14B108K CY14B108M Acronyms Acronym Document Conventions Description Units of Measure AIE alarm interrupt enable BCD binary coded decimal °C degree Celsius BHE byte high enable F farad BLE byte low enable Hz hertz CE CMOS chip enable kHz kilohertz complementary metal oxide semiconductor k kilohm EIA electronic industries alliance MHz megahertz HSB I/O hardware store busy A microampere input/output F microfarad nvSRAM non-volatile static random access memory s micro
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CY14B108K CY14B108M Errata This section describes the errata for the 8 Mb (2048 K × 8 and 1024 K × 16) nvSRAM product families. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. You can also send your related queries directly to nvSRAM@cypress.com.
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CY14B108K CY14B108M Document History Page Document Title: CY14B108K/CY14B108M, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock Document Number: 001-47378 Rev. ECN Orig.
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CY14B108K CY14B108M Document History Page (continued) Document Title: CY14B108K/CY14B108M, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock Document Number: 001-47378 Rev. ECN Orig. of Change Submission Date Description of Change *I 3658005 GVCH 08/10/2012 Updated Real Time Clock Operation (description). Updated Maximum Ratings (Changed “Ambient temperature with power applied” to “Maximum junction temperature”).
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CY14B108K CY14B108M Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.