Specifications

CY14B108K
CY14B108M
Document Number: 001-47378 Rev. *K Page 23 of 36
Figure 9. SRAM Read Cycle 2 (CE and OE Controlled)
[32, 33, 34]
Figure 10. SRAM Write Cycle 1 (WE Controlled)
[32, 34, 35, 36]
Switching Waveforms (continued)
Address ValidAddress
Data Output
Output Data Valid
Standby
Active
High Impedance
CE
OE
BHE, BLE
I
CC
t
HZCE
t
RC
t
ACE
t
AA
t
LZCE
t
DOE
t
LZOE
t
DBE
t
LZBE
t
PU
t
PD
t
HZBE
t
HZOE
Data Output
Data Input
Input Data Valid
High Impedance
Address ValidAddress
Previous Data
t
WC
t
SCE
t
HA
t
BW
t
AW
t
PWE
t
SA
t
SD
t
HD
t
HZWE
t
LZWE
WE
BHE, BLE
CE
Notes
32. BHE
and BLE are applicable for × 16 configuration only.
33. WE
must be HIGH during SRAM read cycles.
34. HSB
must remain HIGH during read and write cycles.
35. If WE
is LOW when CE goes LOW, the outputs remain in the high impedance state.
36. CE
or WE must be V
IH
during address transitions.