Specifications

CY14B108K
CY14B108M
Document Number: 001-47378 Rev. *K Page 24 of 36
Figure 11. SRAM Write Cycle 2 (CE Controlled)
[37, 38, 39, 40]
Figure 12. SRAM Write Cycle 3 (BHE and BLE Controlled)
[ 38, 39, 40, 41, 42]
Switching Waveforms (continued)
Data Output
Data Input
Input Data Valid
High Impedance
Address Valid
Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SA
t
SCE
t
HA
t
BW
t
PWE
Data Output
Data Input
Input Data Valid
High Impedance
Address ValidAddress
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SCE
t
SA
t
BW
t
HA
t
AW
t
PWE
(Not applicable for RTC register writes)
Notes
37. BHE
and BLE are applicable for × 16 configuration only.
38. If WE
is LOW when CE goes LOW, the outputs remain in the high impedance state.
39. HSB
must remain HIGH during read and write cycles.
40. CE
or WE must be V
IH
during address transitions.
41. While there are 19 address lines on the CY14B108K (18 address lines on the CY14B108M), only 13 address lines (A
14
–A
2
) are used to control software modes. The
remaining address lines are don’t care.
42. Only CE
and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.