Specifications

CY14B108K
CY14B108M
Document Number: 001-47378 Rev. *K Page 6 of 36
Device Operation
The CY14B108K/CY14B108M nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B108K/CY14B108M supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See Truth Table For SRAM Operations on page 28
for a complete description of read and write modes.
SRAM Read
The CY14B108K/CY14B108M performs a read cycle when CE
and OE are LOW, and WE and HSB are HIGH. The address
specified on pins A
0–19
or A
0–18
determines which of the
1,048,576 data bytes or 524,288 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
delay of t
AA
(read cycle 1). If the read is initiated by CE or OE,
the outputs are valid at t
ACE
or at t
DOE
, whichever is later (read
cycle 2). The data output repeatedly responds to address
changes within the t
AA
access time without the need for
transitions on any control input pins. This remains valid until
another address change or until CE
or OE is brought HIGH, or
WE
or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE
or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DO
0–15
are written into the memory if it is valid for t
SD
time before the end
of a WE
controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE
, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE
HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE
is left LOW, internal circuitry turns off the output
buffers t
HZWE
after WE goes LOW.
AutoStore Operation
The CY14B108K/CY14B108M stores data to the nvSRAM using
one of three storage operations. These three operations are:
Hardware STORE, activated by the HSB; Software STORE,
activated by an address sequence; AutoStore, on device
power-down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B108K/CY14B108M.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Note If the capacitor is not connected to V
CAP
pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 9. In case AutoStore is enabled without a
capacitor on V
CAP
pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 2. AutoStore Mode
Figure 2 shows the proper connection of the storage capacitor
(V
CAP
) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 19 for the size of the V
CAP
. The voltage
on the V
CAP
pin is driven to V
CC
by a regulator on the chip. A
pull-up should be placed on WE
to hold it inactive during
power-up. This pull-up is effective only if the WE
signal is tristate
during power-up. Many MPUs tristate their controls on power-up.
This should be verified when using the pull-up. When the
nvSRAM comes out of power-on-RECALL, the MPU must be
active or the WE
held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore, and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place.
Hardware STORE (HSB) Operation
The CY14B108K/CY14B108M provides the HSB pin to control
and acknowledge the STORE operations. The HSB
pin is used
to request a Hardware STORE cycle. When the HSB
pin is driven
LOW, the CY14B108K/CY14B108M conditionally initiates a
STORE operation after t
DELAY
. An actual STORE cycle begins
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB
pin also acts as an open drain driver
(internal 100 k weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB
is driven
LOW by any means are given time (t
DELAY
) to complete before
0.1 uF
CC
10 kOhm
V
CAP
WE
V
CAP
V
SS
V
CC