CY14B108K, CY14B108M 8 Mbit (1024K x 8/512K x 16) nvSRAM with Real Time Clock Features ■ Watchdog Timer ■ 25 ns and 45 ns Access Times ■ Clock Alarm with Programmable Interrupts ■ Internally Organized as 1024K x 8 (CY14B108K) or 512K x 16 (CY14B108M) ■ Capacitor or Battery Backup for RTC ■ Industrial Temperature ■ Hands Off Automatic STORE on Power Down with only a Small Capacitor ■ 44 and 54-pin TSOP II Package STORE to QuantumTrap Nonvolatile Elements is Initiated by Software, Device Pin
CY14B108K, CY14B108M Contents Features .............................................................................. 1 Functional Description ...................................................... 1 Logic Block Diagram[1, 2, 3] ............................................ 1 Contents ............................................................................. 2 Pinouts ............................................................................... 3 Device Operation .......................................
CY14B108K, CY14B108M Pinouts Figure 1.
CY14B108K, CY14B108M Table 1. Pin Definitions (continued) Pin Name VCC HSB VCAP I/O Type Description Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%. Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional).
CY14B108K, CY14B108M To reduce unnecessary nonvolatile STOREs, AutoStore, and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress.
CY14B108K, CY14B108M Table 2.
CY14B108K, CY14B108M Data Protection The CY14B108K/CY14B108M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B108K/CY14B108M is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active).
CY14B108K, CY14B108M Real Time Clock Operation nvTime Operation The CY14B108K/CY14B108M offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation.
CY14B108K, CY14B108M The value of OSCF must be reset to ‘0’ when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on. To reset OSCF, set the write bit “W” (in the Flags register at 0xFFFF0) to a “1” to enable writes to the Flag register. Write a “0” to the OSCF bit and then reset the write bit to “0” to disable writes.
CY14B108K, CY14B108M Figure 3. Watchdog Timer Block Diagram Clock Divider Oscillator 32,768 KHz 1 Hz 32 Hz Counter Zero Compare WDF Load Register WDS Q D Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. Note CY14B108K generates valid interrupts only after the Powerup Recall sequence is completed. All events on INT pin must be ignored for tHRECALL duration after powerup.
CY14B108K, CY14B108M Figure 4. RTC Recommended Component Configuration Recommended Values Y1 = 32.768 KHz (12.5 pF) C1 = 12 pF C2 = 69 pF Note: The recommended values for C1 and C2 include board trace capacitance. C1 Y1 C2 Xout Xin Figure 5.
CY14B108K, CY14B108M Table 4.
CY14B108K, CY14B108M Table 5. Register Map Detail Register CY14B108K CY14B108M 0xFFFFF 0x7FFFF Description Time Keeping - Years D7 D6 D5 D4 D3 D2 10s Years D1 D0 Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
CY14B108K, CY14B108M Table 5. Register Map Detail (continued) Register CY14B108K CY14B108M 0xFFFF8 0x7FFF8 OSCEN Description Calibration/Control D7 D6 D5 OSCEN 0 Calibration Sign D4 D3 D2 D1 D0 Calibration Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage.
CY14B108K, CY14B108M Table 5. Register Map Detail (continued) Register CY14B108K CY14B108M 0xFFFF4 0x7FFF4 Description Alarm - Hours D7 D6 M 0 D5 D4 D3 10s Alarm Hours D2 D1 D0 Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M 0xFFFF3 Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value.
CY14B108K, CY14B108M Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Storage Temperature ................................. –65°C to +150°C Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260°C Maximum Accumulated Storage Time At 150°C Ambient Temperature..........................
CY14B108K, CY14B108M Data Retention and Endurance Parameter Description DATAR Data Retention NVC Nonvolatile STORE Operations Min Unit 20 Years 1,000 K Capacitance In the following table, the capacitance parameters are listed. [12] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max Unit 14 pF 14 pF TA = 25°C, f = 1 MHz, VCC = VCC (Typ) Thermal Resistance In the following table, the thermal resistance parameters are listed.
CY14B108K, CY14B108M RTC Characteristics Parameters Description VRTCbat RTC Battery Pin Voltage IBAK[13] RTC Backup Current Min Typ[10] 1.8 3.0 TA (Min) 25°C RTC Capacitor Pin Voltage tOCS RTC Oscillator Time to Start RBKCHG RTC Backup Capacitor Charge Current -Limiting Resistor TA (Min) 1.6 25°C 1.5 TA (Max) 1.4 3.0 1 350 Units 3.6 V 0.35 μA 0.5 μA 3.6 V 3.6 V μA 0.35 TA (Max) VRTCcap[14] Max 3.6 V 2 sec 850 Ω Notes 13. From either VRTCcap or VRTCbat. 14.
CY14B108K, CY14B108M AC Switching Characteristics Parameters Cypress Alt Parameters Parameters SRAM Read Cycle tACE tACS [15] tRC tRC tAA tAA [16] tDOE tOE [16] tOH tOHA tLZCE [12, 17] tLZ tHZCE [12, 17] tHZ [12, 17] tLZOE tOLZ tHZOE [12, 17] tOHZ tPU [12] tPA [12] tPD tPS tDBE tLZBE[12] [12] tHZBE SRAM Write Cycle tWC tWC tWP tPWE tSCE tCW tSD tDW tHD tDH tAW tAW tSA tAS tHA tWR [12, 17,18] tHZWE tWZ tLZWE [12, 17] tOW tBW - 25 ns Description Chip Enable Access Time Read Cycle Time Address Access Time O
CY14B108K, CY14B108M Switching Waveforms Figure 8. SRAM Read Cycle 2: CE and OE Controlled[3, 15, 19] Address Address Valid tRC tACE CE tHZCE tAA tLZCE tHZOE tDOE OE tHZBE tLZOE tDBE BHE, BLE tLZBE Data Output ICC High Impedance Output Data Valid tPU tPD Active Standby Figure 9.
CY14B108K, CY14B108M Switching Waveforms Figure 10. SRAM Write Cycle 2: CE Controlled[3, 18, 19, 20] tWC Address Valid Address tSA tSCE tHA CE tBW BHE, BLE tPWE WE tHD tSD Input Data Valid Data Input High Impedance Data Output Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[5, 18, 19, 20, 21] (Not applicable for RTC register writes) tWC Address Address Valid tSCE CE tSA tHA tBW BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output Note 21.
CY14B108K, CY14B108M AutoStore/Power Up RECALL Parameters tHRECALL [22] tSTORE [23] CY14B108K/CY14B108M Description Min Max Power Up RECALL Duration Unit 20 ms STORE Cycle Duration 8 ms tDELAY [24] Time Allowed to Complete SRAM Write Cycle 25 ns VSWITCH Low Voltage Trigger Level tVCCRISE[12] VCC Rise Time VHDIS[12] HSB Output Disable Voltage 1.9 V tLZHSB[12] HSB To Output Active Time 5 μs tHHHD[12] HSB High Active Time 500 ns 2.65 V μs 150 Switching Waveforms Figure 12.
CY14B108K, CY14B108M Software Controlled STORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [27, 28] Parameters tRC tSA tCW tHA tRECALL tSS [29, 30] 25 ns Description Min 25 0 20 0 STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time 45 ns Max Min 45 0 30 0 200 100 Unit Max ns ns ns ns μs μs 200 100 Switching Waveforms Figure 13.
CY14B108K, CY14B108M Hardware STORE Cycle Parameters CY14B108K/CY14B108M Description Min tDHSB HSB To Output Active Time when write latch not set tPHSB Hardware STORE Pulse Width Max 25 Unit ns 15 ns Switching Waveforms Figure 15.
CY14B108K, CY14B108M Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations.
CY14B108K, CY14B108M Part Numbering Nomenclature CY14 B 108 K - ZSP 25 X I T Option: T - Tape & Reel Blank - Std. Pb-Free Package: ZSP - 44 TSOP II ZSP - 54 TSOP II Temperature: I - Industrial (–40 to 85°C) Speed: 25 - 25 ns 45 - 45 ns Data Bus: K - x8 + RTC M - x16 + RTC Density: 108 - 8 Mb Voltage: B - 3.0V 14 - NVSRAM Cypress Document #: 001-47378 Rev.
CY14B108K, CY14B108M Ordering Information Speed (ns) 25 45 Ordering Code Package Diagram Package Type CY14B108K-ZS25XIT 51-85087 44-pin TSOPII CY14B108K-ZS25XI 51-85187 44-pin TSOPII CY14B108M-ZSP25XIT 51-85160 54-pin TSOPII CY14B108M-ZSP25XI 51-85160 54-pin TSOPII CY14B108K-ZS45XIT 51-85087 44-pin TSOPII CY14B108K-ZS45XI 51-85187 44-pin TSOPII CY14B108M-ZSP45XIT 51-85160 54-pin TSOPII CY14B108M-ZSP45XI 51-85160 54-pin TSOPII Operating Range Industrial All the above parts are
CY14B108K, CY14B108M Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) 51-85087 *B Document #: 001-47378 Rev.
CY14B108K, CY14B108M Package Diagrams (continued) Figure 18. 54-Pin TSOP II (51-85160) 51-85160 ** Document #: 001-47378 Rev.
CY14B108K, CY14B108M Document History Page Document Title: CY14B108K, CY14B108M 8 Mbit (1024K x 8/512K x 16) nvSRAM with Real Time Clock Document Number: 001-47378 Rev. ECN No. Orig.
CY14B108K, CY14B108M Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors USB image.cypress.com psoc.cypress.