nvSRAM Specification Sheet

PRELIMINARY
CY14B108L, CY14B108N
Document #: 001-45523 Rev. *B Page 12 of 24
Figure 8. SRAM Write Cycle #2: CE
Controlled
[3, 14, 15, 16]
Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled
[3, 14, 15, 16]
Data Output
Data Input
Input Data Valid
High Impedance
Address Valid
Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SA
t
SCE
t
HA
t
BW
t
PWE
Data Output
Data Input
Input Data Valid
High Impedance
Address ValidAddress
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SCE
t
SA
t
BW
t
HA
t
AW
t
PWE
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