nvSRAM Specification Sheet

PRELIMINARY
CY14B108L, CY14B108N
Document #: 001-45523 Rev. *B Page 14 of 24
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.
[22, 23]
Parameters Description
20 ns 25 ns 45 ns
Unit
Min Max Min Max Min Max
t
RC
STORE/RECALL Initiation Cycle Time 20 25 45 ns
t
SA
Address Setup Time 0 0 0 ns
t
CW
Clock Pulse Width 15 20 30 ns
t
HA
Address Hold Time 0 0 0 ns
t
RECALL
RECALL Duration 200 200 200 μs
Switching Waveforms
Figure 11. CE and OE Controlled Software STORE/RECALL Cycle
[23]
Figure 12. Autostore Enable/Disable Cycle
t
RC
t
RC
t
SA
t
CW
t
CW
t
SA
t
HA
t
LZCE
t
HZCE
t
HA
t
HA
t
HA
t
DELAY
t
STORE
/t
RECALL
t
HHHD
t
LZHSB
High Impedance
Address #1 Address #6Address
CE
OE
HSB(STOREonly)
DQ (DATA)
RWI
t
RC
t
RC
t
SA
t
CW
t
CW
t
SA
t
HA
t
LZCE
t
HZCE
t
HA
t
HA
t
HA
t
DELAY
Address #1 Address #6Address
CE
OE
DQ (DATA)
t
SS
Notes
22. The software sequence is clocked with CE
controlled or OE controlled reads.
23. The six consecutive addresses must be read in the order listed in Table 2 on page 6. WE
must be HIGH during all six consecutive cycles.
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