nvSRAM Specification Sheet

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CY14B256K

256 Kbit (32K x 8) nvSRAM with Real Time Clock

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06431 Rev. *H Revised February 24, 2009

Features

■ 25 ns, 35 ns, and 45 ns access times

■ Pin compatible with STK17T88

■ Data integrity of Cypress nvSRAM combined with full featured

Real Time Clock

❐ Low power, 350 nA RTC current

❐ Capacitor or battery backup for RTC

■ Watchdog timer

■ Clock alarm with programmable interrupts

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap™ initiated by software, device pin, or

on power down

■ RECALL to SRAM initiated by software or on power up

■ Infinite READ, WRITE, and RECALL cycles

■ High reliability

❐ Endurance to 200K cycles

❐ Data retention: 20 years at 55°C

■ Single 3V operation with tolerance of +20%, -10%

■ Commercial and industrial temperature

■ 48-Pin SSOP (ROHS compliant)

Functional Description

The Cypress CY14B256K combines a 256 Kbit nonvolatile static

RAM with a full-featured real time clock in a monolithic integrated

circuit. The embedded nonvolatile elements incorporate

QuantumTrap technology producing the world’s most reliable

nonvolatile memory. The SRAM is read and written an infinite

number of times, while independent, nonvolatile data resides in

the nonvolatile elements.

The real time clock function provides an accurate clock with leap

year tracking and a programmable high accuracy oscillator. The

alarm function is programmable for one time alarms or periodic

seconds, minutes, hours, or days. There is also a programmable

watchdog timer for process control.

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

512 X 512

QuantumTrap

512 X 512

STORE

RECALL

COLUMN IO

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

RTC

MUX

INT

RTCbat

RTCcap

Logic Block Diagram

[+] Feedback

Summary of content (28 pages)

PAGE 1
CY14B256K 256 Kbit (32K x 8) nvSRAM with Real Time Clock Features ■ High reliability ❐ Endurance to 200K cycles ❐ Data retention: 20 years at 55°C ■ 25 ns, 35 ns, and 45 ns access times ■ Pin compatible with STK17T88 ■ Single 3V operation with tolerance of +20%, -10% ■ Data integrity of Cypress nvSRAM combined with full featured Real Time Clock ❐ Low power, 350 nA RTC current ❐ Capacitor or battery backup for RTC ■ Commercial and industrial temperature ■ 48-Pin SSOP (ROHS compliant) ■ Watc
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CY14B256K Pin Configurations Figure 1.
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CY14B256K Device Operation automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. The CY14B256K nvSRAM consists of two functional components paired in the same physical cell. The components are SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM.
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CY14B256K tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. It is important to use READ cycles and not WRITE cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for READ and WRITE operations.
PAGE 5
CY14B256K Low Average Active Power Best Practices CMOS technology provides the CY14B256K the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 3 shows the relationship between ICC and READ and/or WRITE cycle time. Worst case current consumption is shown for commercial temperature range, VCC = 3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled.
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CY14B256K Table 1.
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CY14B256K Real Time Clock Operation nvTIME Operation The CY14B256K consists of internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and the clock and timer information registers prevent accessing transitional internal clock data during a read or write operation.
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CY14B256K Calibrating the Clock The RTC is driven by a quartz controlled oscillator with a nominal frequency of 32.768 kHz. Clock accuracy depends on the quality of the crystal and calibration. The crystal oscillators typically have an error of +20ppm to +35ppm. However, CY14B256K employs a calibration circuit that improves the accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5 seconds to -5 seconds per month.
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CY14B256K Figure 4. Watchdog Timer Block Diagram Clock Divider Oscillator 32,768 KHz 1 Hz 32 Hz Counter Zero Compare WDF register is enabled (set to ‘1’). After an interrupt source is active, two programmable bits, H/L and P/L, determine the behavior of the output pin driver on INT pin. These two bits are located in the Interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms.
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CY14B256K Figure 5. Interrupt Block Diagram WDF Watchdog Timer WIE P/L PF Power Monitor VCC Pin Driver PFE INT VINT H/L VSS AF Clock Alarm WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low AIE Figure 6. RTC Recommended Component Configuration DQ 0 A3 A2 A1 C2 Y1 RF C1 A0 X1 X2 Recommended Values: Y1 = 32.
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CY14B256K Table 3.
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CY14B256K Table 4. Register Map Detail Time Keeping - Years D7 D6 0x7FFF D5 D4 D3 D2 10s Years D1 D0 Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. Time Keeping - Months 0x7FFE D7 D6 D5 D4 0 0 0 10s Month D3 D2 D1 D0 Months Contains the BCD digits of the month.
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CY14B256K Table 4. Register Map Detail (continued) Calibration/Control 0X7FF8 OSCEN D7 D6 D5 OSCEN 0 Calibration Sign D4 D3 D2 D1 D0 Calibration Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.
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CY14B256K Table 4. Register Map Detail (continued) Alarm - Hours 0x7FF4 D7 D6 D5 M D4 D3 D2 10s Alarm Hours D1 D0 Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value.
PAGE 15
CY14B256K Maximum Ratings Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Surface Mount Pb Soldering Temperature (3 Seconds).......................................... +260°C Storage Temperature ................................. –65°C to +150°C DC Output Current (1 output at a time, 1s duration) ...
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CY14B256K Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 20 Years NVC Nonvolatile STORE Operations 200 K Capacitance These parameters are guaranteed but not tested. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V Max Unit 7 pF 7 pF 48-SSOP Unit 32.9 °C/W 25.56 °C/W Thermal Resistance These parameters are guaranteed but not tested.
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CY14B256K AC Switching Characteristics Parameter Cypress Parameter 25 ns Description Alt.
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CY14B256K AC Switching Characteristics (continued) Parameter Cypress Parameter 25 ns Description Alt.
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CY14B256K AutoStore or Power Up RECALL Parameter tHRECALL [17] tSTORE CY14B256K Description Min Max Power Up RECALL Duration [18, 19] STORE Cycle Duration VSWITCH Low Voltage Trigger Level tVCCRISE VCC Rise Time Unit 40 ms Commercial 12.5 ms Industrial 15 ms 2.65 V μs 150 Figure 12.
PAGE 20
CY14B256K Software Controlled STORE/RECALL Cycles [20, 21] Parameter Alt. Parameter Description 25 ns Min 35 ns Max Min Max 45 ns Min Max Unit tRC tAVAV STORE/RECALL Initiation Cycle Time 25 35 45 ns tSA tAVEL Address Setup Time 0 0 0 ns tCW tELEH Clock Pulse Width 20 25 30 ns tHA tEHAX Address Hold Time 1 1 1 ns tRECALL RECALL Duration 170 170 170 μs Figure 13.
PAGE 21
CY14B256K Hardware STORE Cycle Parameter Alt. Parameter tDELAY [22] tPHSB tHLHX CY14B256K Description Min Max Time Allowed to Complete SRAM Cycle 1 70 Hardware STORE Pulse Width 15 Unit μs ns Figure 15. Hardware STORE Cycle W3+6% +/+; +6% ,1 W6725( W+/%/ +6% 287 +,*+ ,03('$1&( +,*+ ,03('$1&( W '(/$< '$7$ 9$/,' '4 '$7$ 287 '$7$ 9$/,' Soft Sequence Commands Parameter tSS [23, 24] CY14B256K Description Min Max Soft Sequence Processing Time 70 Unit μs Figure 16.
PAGE 22
CY14B256K RTC Characteristics Parameter IBAK [25] Description Test Conditions RTC Backup Current Min Max Unit Commercial 300 nA Industrial 350 nA VRTCbat [26] RTC Battery Pin Voltage 1.8 3.3 V VRTCcap [27] RTC Capacitor Pin Voltage 1.2 2.7 V 10 sec 5 sec tOCS RTC Oscillator Time to Start At Min Temperature from Power up or Enable At 25°C Temperature from Power up or Enable Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations.
PAGE 23
CY14B256K Part Numbering Nomenclature CY 14 B 256 K - SP 25 X C T Option: T-Tape and Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Pb-Free Package: SP - 48-SSOP Voltage: B - 3.0V Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns Data Bus: K - x8 + RTC Density: 256 - 256 Kb nvSRAM 14 - AutoStore + Software Store + Hardware Store Cypress Document Number: 001-06431 Rev.
PAGE 24
CY14B256K Ordering Information All the below mentioned parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
PAGE 25
CY14B256K Package Diagrams Figure 17. 48-Pin Shrunk Small Outline Package (51-85061) 51-85061-*C Document Number: 001-06431 Rev.
PAGE 26
CY14B256K Document History Page Document Title: CY14B256K 256 Kbit (32K x 8) nvSRAM with Real Time Clock Document Number: 001-06431 Rev. ECN Orig. of Change Submission Date ** 425138 TUP See ECN Description of Change New data sheet *A 437321 TUP See ECN Show data sheet on external Web *B 471966 TUP See ECN Changed VIH(min) from 2.2V to 2.
PAGE 27
CY14B256K Document Title: CY14B256K 256 Kbit (32K x 8) nvSRAM with Real Time Clock Document Number: 001-06431 Rev. ECN Orig. of Change Submission Date *H 2663934 GVCH/PYRS 02/24/09 Document Number: 001-06431 Rev. *H Description of Change Updated Features section Updated pin definition of WE pin Updated “Reading the clock”, “Backup Power”, “Stopping and starting the Oscillator” and “Alarm” descriptions under RTC operation Modified “Figure 4.
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CY14B256K Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.