2-Mbit nvSRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY14E102L

ADVANCE

CY14E102L, CY14E102N

2-Mbit (256K x 8/128K x 16) nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-45755 Rev. *A Revised June 27, 2008

Features

■ 15 ns, 20 ns, 25 ns, and 45 ns access times

■ Internally organized as 256K x 8 (CY14E102L) or 128K x 16

(CY14E102N)

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap

™

nonvolatile elements initiated by

software, device pin, or AutoStore

™

on power down

■ RECALL to SRAM initiated by software or power up

■ Infinite read, write, and recall cycles

■ 200,000 STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 5V +10% operation

■ Commercial and Industrial temperatures

■ 48-pin FBGA, 44 and 54-pin TSOP II packages

■ Pb-free and RoHS compliance

Functional Description

The Cypress CY14E102L/CY14E102N is a fast static RAM, with

a nonvolatile element in each memory cell. The memory is

organized as 256K words of 8 bits each or 128K words of 16 bits

each. The embedded nonvolatile elements incorporate

QuantumTrap technology, producing the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while independent nonvolatile data reside in the highly

reliable QuantumTrap cell. Data transfers from the SRAM to the

nonvolatile elements (the STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM (the RECALL operation) from the nonvolatile memory.

Both the STORE and RECALL operations are also available

under software control.

Note

1. Address A

- A

and Data DQ0 - DQ7 for x8 configuration, Address A

- A

and Data DQ0 - DQ15 for x16 configuration.

- A

Address

CAP

DQ0 - DQ7

HSB

CY14E102L

BHE

BLE

Logic Block Diagram

[1]

CY14E102N

[+] Feedback

Summary of content (21 pages)

PAGE 1
ADVANCE CY14E102L, CY14E102N 2-Mbit (256K x 8/128K x 16) nvSRAM Features Functional Description ■ 15 ns, 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 256K x 8 (CY14E102L) or 128K x 16 (CY14E102N) ■ Hands off automatic STORE on power down with only a small capacitor ■ STORE to QuantumTrap™ nonvolatile elements initiated by software, device pin, or AutoStore™ on power down ■ RECALL to SRAM initiated by software or power up ■ Infinite read, write, and recall cycles ■ 200,000
PAGE 2
CY14E102L, CY14E102N ADVANCE Pinouts Figure 1.
PAGE 3
CY14E102L, CY14E102N ADVANCE Pinouts (continued) Figure 3.
PAGE 4
CY14E102L, CY14E102N ADVANCE The CY14E102L/CY14E102N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture all cells are stored and recalled in parallel.
PAGE 5
CY14E102L, CY14E102N ADVANCE Hardware RECALL (Power Up) The software sequence may be clocked with CE controlled READs or OE controlled READs. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important to use READ cycles and not WRITE cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the READ and WRITE operation.
PAGE 6
CY14E102L, CY14E102N ADVANCE Table 1.
PAGE 7
CY14E102L, CY14E102N ADVANCE Maximum Ratings Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260°C Storage Temperature ................................. –65°C to +150°C Output Short Circuit Current [8] ....................................
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CY14E102L, CY14E102N ADVANCE Capacitance The following table lists the capacitance parameters.[11] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0V Max Unit 7 pF 7 pF Thermal Resistance The following table lists the thermal resistance parameters.
PAGE 9
CY14E102L, CY14E102N ADVANCE AC Switching Characteristics The following table lists the AC switching characteristics.
PAGE 10
CY14E102L, CY14E102N ADVANCE AutoStore and Power Up RECALL Parameters CY14E102L/CY14E102N Description Min Unit Max tHRECALL [16] Power Up RECALL Duration 20 ms STORE Cycle Duration 15 ms VSWITCH Low Voltage Trigger Level 4.4 V tVCCRISE VCC Rise Time tSTORE [17] μs 150 Software Controlled STORE and RECALL Cycle The following table lists the software controlled STORE and RECALL cycle parameters.
PAGE 11
CY14E102L, CY14E102N ADVANCE Switching Waveforms Figure 5. SRAM Read Cycle #1: Address Controlled[12, 13, 23] tRC ADDRESS t AA t OHA DQ (DATA OUT) DATA VALID Figure 6. SRAM Read Cycle #2: CE and OE Controlled[12, 23, 25] tRC ADDRESS tLZCE CE tACE tPD tHZCE OE tLZOE t HZOE tDOE BHE , BLE tLZBE DQ (DATA OUT) t PU ICC tHZCE tHZBE tDBE DATA VALID ACTIVE STANDBY Notes 23. HSB must remain HIGH during READ and WRITE cycles. 24. CE or WE must be >VIH during address transitions. 25.
PAGE 12
CY14E102L, CY14E102N ADVANCE Switching Waveforms (continued) Figure 7. SRAM Write Cycle #1: WE Controlled[13, 21, 22, 23] t WC ADDRESS t HA t SCE CE t AW t SA t PWE WE t BW BHE , BLE t SD t HD DATA VALID DATA IN tHZWE DATA OUT t LZWE HIGH IMPEDANCE PREVIOUS DATA Figure 8. SRAM Write Cycle #2: CE Controlled[13, 21, 22, 23] tWC ADDRESS tSA tSCE CE tHA tAW WE BHE , BLE tPWE tBW tSD DATA IN DATA OUT Document Number: 001-45755 Rev.
PAGE 13
CY14E102L, CY14E102N ADVANCE Switching Waveforms (continued) Figure 9. AutoStore or Power Up RECALL[26] No STORE occurs without atleast one SRAM write STORE occurs only if a SRAM write has happened VCC VSWITCH tVCCRISE AutoStore tSTORE tSTORE POWER-UP RECALL tHRECALL tHRECALL Read & Write Inhibited Figure 10. CE Controlled Software STORE/RECALL Cycle[19] Note 26. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. Document Number: 001-45755 Rev.
PAGE 14
CY14E102L, CY14E102N ADVANCE Switching Waveforms (continued) Figure 11. OE Controlled Software STORE/RECALL Cycle[19] tRC ADDRESS # 1 ADDRESS CE tAS ADDRESS # 6 tCW OE tGHAX DATA VALID a a DQ (DATA) t STORE / t RECALL DATA VALID a a a a a a a a a a a a tRC HIGH IMPEDANCE Figure 12. Hardware STORE Cycle[22] Figure 13. Soft Sequence Processing[20, 21] tSS Document Number: 001-45755 Rev.
PAGE 15
CY14E102L, CY14E102N ADVANCE Ordering Information Speed (ns) 15 20 Ordering Code Package Diagram Package Type Operating Range CY14B102L-ZS15XCT 51-85087 44-pin TSOP II Commercial CY14E102L-ZS15XIT 51-85087 44-pin TSOP II Industrial CY14E102L-ZS15XI 51-85087 44-pin TSOP II CY14E102L-BA15XCT 51-85128 48-ball FBGA Commercial Industrial CY14E102L-BA15XIT 51-85128 48-ball FBGA CY14E102L-BA15XI 51-85128 48-ball FBGA CY14E102L-ZSP15XCT 51-85160 54-pin TSOP II Commercial CY14E102L-Z
PAGE 16
CY14E102L, CY14E102N ADVANCE Ordering Information (continued) Speed (ns) 25 45 Ordering Code Package Diagram Package Type Operating Range CY14E102L-ZS25XCT 51-85087 44-pin TSOP II Commercial CY14E102L-ZS25XIT 51-85087 44-pin TSOP II Industrial CY14E102L-ZS25XI 51-85087 44-pin TSOP II CY14E102N-BA25XCT 51-85128 48-ball FBGA Commercial Industrial CY14E102L-BA25XIT 51-85128 48-ball FBGA CY14E102L-BA25XI 51-85128 48-ball FBGA CY14E102L-ZSP25XCT 51-85160 54-pin TSOP II Commercial
PAGE 17
CY14E102L, CY14E102N ADVANCE Part Numbering Nomenclature CY 14 E 102 L - ZS P 15 X C T Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Pb-Free P - 54 Pin Blank - 44 Pin Package: BA - 48 FBGA ZS - TSOP II Voltage: E - 5.0V Data Bus: L - x8 N - x16 Speed: 15 - 15 ns 20 - 20 ns 25 - 25 ns 45 - 45 ns Density: 102 - 2 Mb NVSRAM 14 - Auto Store + Software Store + Hardware Store Cypress Document Number: 001-45755 Rev.
PAGE 18
CY14E102L, CY14E102N ADVANCE Package Diagrams Figure 14. 44-Pin TSOP II DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 1 23 10.262 (0.404) 10.058 (0.396) 11.938 (0.470) 11.735 (0.462) 22 EJECTOR PIN 44 TOP VIEW 0.800 BSC (0.0315) OR E K X A SG BOTTOM VIEW 0.400(0.016) 0.300 (0.012) 10.262 (0.404) 10.058 (0.396) BASE PLANE 0.210 (0.0083) 0.120 (0.0047) 0°-5° 0.10 (.004) Document Number: 001-45755 Rev. *A 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 18.517 (0.729) 18.313 (0.
PAGE 19
CY14E102L, CY14E102N ADVANCE Package Diagrams (continued) Figure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 10.00±0.10 10.00±0.10 1 F G H H 1.875 A A B 0.75 6.00±0.10 0.53±0.05 B 0.15 C 0.21±0.05 0.25 C 3.75 6.00±0.10 0.15(4X) Document Number: 001-45755 Rev. *A 1.20 MAX 0.
PAGE 20
ADVANCE Package Diagrams CY14E102L, CY14E102N (continued) Figure 16. 54-Pin TSOP II 51-85160-** Document Number: 001-45755 Rev.
PAGE 21
ADVANCE CY14E102L, CY14E102N Document History Page Document Title: CY14E102L/CY14E102N 2-Mbit (256K x 8/128K x 16) nvSRAM Document Number: 001- 45755 REV. ECN NO. Orig. of Change ** 2470086 GVCH *A 2522209 GVCH/ AESA Submission Date Description of Change New Data Sheet 06/27/2008 Added 20 ns access speed information in “Features”. Added ICC1 for tRC=20 ns for both industrial and Commercial temperature Grade. Updated Thermal resistance values for 48-FBGA, 44-TSOP II and 54-TSOP II Packages.