Spread Spectrum Clock Generator Specification Sheet

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Spread Spectrum Clock Generator

CY25566

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-07429 Rev. *B Revised October 26, 2005

Features

• 25- to 200-MHz operating frequency range

• Wide range of spread selections (9)

• Accepts clock or crystal inputs

• Provides four clocks

— SSCLK1a

— SSCLK1b

— SSCLK2

—REFOUT

• Low-power dissipation

— 3.3V = 70 mW (typical @ 40 MHz, no load)

• Center spread modulation

• Low cycle-to cycle jitter

• 16-pin SOIC package

Applications

• High-resolution VGA controllers

• LCD panels and monitors

• Printers and MFPs

Benefits

• Peak EMI reduction by 8 to 16 dB

• Fast time to market

• Cost reduction

Block Diagram

Pin Configuration

116

XI N/CLKI N

REFOFF

VDD

VSS

SSCLK1a

REFOUT

SSCLK1b

SSCC

VSS

SSCLK2

XOUT

CY25566

REFERENCE

DIVIDER

Loop

Filter

MODULATION

CONTROL

INPUT

DECODER

LOGIC

FEEDBACK

DIVIDER

vco

DIVIDER

MUX

SSCLK1a

S0S1

20 K

20 K20 K

20 K

SSCC

VDD

VSS

Xout

Xin/

CLK

VDDVDD

VSSVSS

300K

VSS

RANGE

CONTROL

S3S2

SSCLK1b

SSCLK2

REFOUT

REFOFF

[+] Feedback

Summary of content (9 pages)

PAGE 1
CY25566 Spread Spectrum Clock Generator Features • • • • • Center spread modulation • Low cycle-to cycle jitter • 16-pin SOIC package 25- to 200-MHz operating frequency range Wide range of spread selections (9) Accepts clock or crystal inputs Provides four clocks — SSCLK1a Applications • High-resolution VGA controllers • LCD panels and monitors • Printers and MFPs — SSCLK1b — SSCLK2 Benefits — REFOUT • Low-power dissipation — 3.
PAGE 2
CY25566 Pin Description Pin Name Type Description 1 XIN/CLKIN I Clock or Crystal connection input. Refer to Table 1, Table 2, and Table 3 for input frequency range selection. 2 REFOFF I Input pin enables REFOUT clock at pin 3. REFOFF 400KΩ internal pull-up resistor. Logic “0” enables REFOUT, logic “1” disables REFOUT. Default = disabled. 3 REFOUT O Buffered, non-modulated output clock derived from XIN/CLKIN input frequency. There is a 180° phase shift from XIN to REFOUT.
PAGE 3
CY25566 Control Logic Structures SSCLK1a/b SSCLK1a and SSCLK1b are spread spectrum clock outputs used for the purpose of reducing EMI in digital systems. SSCLK1a and SSCLK1b can be connected in several different ways to provide flexibility in application designs. Each clock can drive separate nets with a capacitative load up to 15 pF each or connected together to provide drive to a single net with a capacitative load as high as 33 pF.
PAGE 4
CY25566 Modulation Rate Spread Spectrum clock generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition from Fmin to Fmax and back to Fmin is the period of the Modulation Rate, Tmod. Modulation Rates of SSCG clocks are generally referred to in terms of frequency or Fmod = 1/Tmod.
PAGE 5
CY25566 Table 1. Frequency and Bandwidth Selection Chart (Group 1)(Low Frequency (1x) Selection Chart) 25–50 MHz (Low Range) XIN/CLK (MHz) S1 = M S0 = M S1 = M S0 = 0 S1 = 1 S0 = 0 S1 = 0 S0 = 0 S1 = 0 S0 = M 25–35 4.3 3.8 3.4 2.9 2.8 35–40 3.9 3.5 3.1 2.5 2.4 40–45 3.7 3.3 2.8 2.4 2.3 45–50 3.4 3.1 2.6 2.2 2.1 S3 S2 0 0 50–100 MHz (High Range) XIN/CLK (MHz) S1 = 1 S0 = M S1 = 0 S0 = 1 S1 = 1 S0 = 1 S1 = M S0 = 1 50–60 2.9 2.1 1.5 1.2 60–70 2.8 2.0 1.4 1.
PAGE 6
CY25566 Application Schematic In this example, the CY25566 is being driven by a 75-MHz reference clock. VDD = 3.30 VDC. S0 = 0 and S1 = 0 are programmed to select a BW of 2.5%. (Refer to Table 1 and 2.) SSCLK1b = 75 MHz @ 2.5% center spread modulation. S2 = 0 and S3 = 1 are programmed to select the Group 2 range. REFOUT = 37.5 MHz non-modulated clock. SSCLK1a = 75 MHz @ 2.5% center spread modulation. SSCLK 2 = 37.5 MHz @ 2.5% center spread modulation. VDD 0.
PAGE 7
CY25566 Absolute Maximum Ratings[1, 2] Supply Voltage (VDD: .......................................................+6V Operating Temperature: ...................................... 0°C to 70°C Storage Temperature .................................. –65°C to +150°C Table 4. DC Electrical Characteristics VDD = 3.3V, Temp. = 25°C, unless otherwise noted Parameter Description VDD Power Supply Range Conditions ±10% Min. Typ. Max. Unit 2.97 3.3 3.63 V VINH Input High Voltage S0 and S1 only. 0.
PAGE 8
CY25566 Ordering Information Part Number Package Type Product Flow CY25566SC 16-pin SOIC Commercial, 0° to 70°C CY25566SCT 16-pin SOIC–Tape and Reel Commercial, 0° to 70°C Package Drawing and Dimensions 16-Lead (150-Mil) SOIC S16.15 16 Lead (150 Mil) SOIC PIN 1 ID 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16 0.386[9.804] 0.393[9.982] 0.010[0.
PAGE 9
CY25566 Document Title:CY25566 Spread Spectrum Clock Generator Document Number: 38-07429 Rev. ECN No. Issue Date Orig. of Change ** 115771 07/01/02 OXC New Data Sheet *A 122705 12/30/02 RBI Added power up requirements to maximum ratings information. *B 404070 See ECN RGL Minor Change: Typo error on table 1, column 2 , S0 = 0 (not M) Document #: 38-07429 Rev.