Static RAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY62148EV30

MoBL

CY62148EV30

4-Mbit (512K x 8) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05576 Rev. *G Revised August 4, 2008

Features

■ Very high speed: 45 ns

❐ Wide voltage range: 2.20V to 3.60V

■ Temperature ranges

❐ Industrial: –40°C to +85°C

❐ Automotive-A: –40°C to +85°C

■ Pin compatible with CY62148DV30

■ Ultra low standby power

❐ Typical standby current: 1 μA

❐ Maximum standby current: 7 μA (Industrial)

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

■ Easy memory expansion with CE, and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

■ Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin

SOIC

[1]

packages

Functional Description

The CY62148EV30

[2]

is a high performance CMOS static RAM

organized as 512K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL

) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption. Placing the device into standby mode reduces

power consumption by more than 99 percent when deselected

(CE

HIGH). The eight input and output pins (IO

through IO

) are

placed in a high impedance state when the device is deselected

(CE HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE

LOW and WE LOW).

To write to the device, take Chip Enable (CE

) and Write Enable

(WE

) inputs LOW. Data on the eight IO pins (IO

through IO

) is

then written into the location specified on the address pins (A

through A

To read from the device, take Chip Enable (CE

) and Output

Enable (OE

) LOW while forcing Write Enable (WE) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins appear on the IO pins.

Notes

1. SOIC package is available only in 55 ns speed bin.

2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

Logic Block Diagram

SENSE AMPS

POWER

DOWN

ROW DECODER

COLUMN DECODER

512K x 8

ARRAY

INPUT BUFFER

[+] Feedback

Summary of content (12 pages)

PAGE 1
MoBL® CY62148EV30 4-Mbit (512K x 8) Static RAM Features Functional Description The CY62148EV30[2] is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption.
PAGE 2
MoBL® CY62148EV30 Pin Configuration [1, 3] 36-Ball VFBGA Pinout 32-Pin SOIC/TSOP II Pinout Top View Top View A6 A8 A A7 IO 0 B IO 1 C VSS Vcc D VCC Vss E IO 2 F A0 A1 NC A3 IO 4 A2 WE A4 NC A5 IO 5 IO 6 A18 A17 IO 7 OE CE A16 A15 IO 3 G A9 A10 A11 A12 A13 A14 H A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE IO7 IO6 IO5 IO4 IO
PAGE 3
MoBL® CY62148EV30 DC Input Voltage [5, 6] .....................–0.3V to VCC(max) + 0.3V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied .............................................. 55°C to +125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage...................................
PAGE 4
MoBL® CY62148EV30 Capacitance (For All packages) [10] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max TA = 25°C, f = 1 MHz, VCC = VCC(typ) Unit 10 pF 10 pF Thermal Resistance [10] Parameter Test Conditions VFBGA Package TSOP II Package SOIC Package Unit Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 72 75.13 55 °C/W 8.86 8.
PAGE 5
MoBL® CY62148EV30 Switching Characteristics (Over the Operating Range) [12] Parameter Description - 55 [1] - 45 (Ind’l/Auto-A) Min Max Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 55 ns tDOE OE LOW to Data Valid 22 25 ns tLZOE 45 OE LOW to Low Z tHZOE [13] OE HIGH to High Z tLZCE CE LOW to Low Z CE HIGH to High Z tPU CE LOW to Power Up Write Cycle 10 55 10 ns 20 10 18 0 ns ns 2
PAGE 6
MoBL® CY62148EV30 Switching Waveforms Figure 1. Read Cycle No. 1 (Address Transition Controlled) [16, 17] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 2. Read Cycle No. 2 (OE Controlled) [17, 18] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Figure 3. Write Cycle No.
PAGE 7
MoBL® CY62148EV30 Switching Waveforms (continued) Figure 4. Write Cycle No. 2 (CE Controlled) [19, 20] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Figure 5. Write Cycle No.
PAGE 8
MoBL® CY62148EV30 Ordering Information Speed (ns) Package Diagram Ordering Code 45 55 Operating Range Package Type CY62148EV30LL-45BVXI 51-85149 36-ball Very Fine Pitch Ball Grid Array (Pb-free) CY62148EV30LL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free) Industrial CY62148EV30LL-45ZSXA 51-85095 32-pin Thin Small Outline Package II (Pb-free) CY62148EV30LL-55SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Automotive-A Industrial Contact your local Cypress sales
PAGE 9
MoBL® CY62148EV30 Package Diagrams (continued) Figure 7. 32-pin TSOP II (51-85095) 51-85095-** Document #: 38-05576 Rev.
PAGE 10
MoBL® CY62148EV30 Package Diagrams (continued) Figure 8. 32-pin (450 MIL) Molded SOIC (51-85081) 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] SEATING PLANE 51-85081-*B Document #: 38-05576 Rev.
PAGE 11
MoBL® CY62148EV30 Document History Page Document Title: CY62148EV30 MoBL® 4-Mbit (512K x 8) Static RAM Document Number: 38-05576 Revision ECN Submission Orig. of Date Change ** 223225 See ECN AJU New data sheet *A 247373 See ECN SYT Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Changed VCC stabilization time in footnote #7 from 100 μs to 200 μs Changed ICCDR from 2.0 μA to 2.
PAGE 12
MoBL® CY62148EV30 Document Title: CY62148EV30 MoBL® 4-Mbit (512K x 8) Static RAM Document Number: 38-05576 Revision ECN Submission Orig. of Date Change Description of Change *F 987940 See ECN VKN Changed VOL spec from 0.4V to 0.2V for SOIC package at IOL = 0.1 mA Changed VIL spec from 0.6V to 0.4V for SOIC package at VCC = 2.2V to 2.7V Updated footnote 8 Made footnote 9 applicable for both ISB2 and ICCDR *G 2548575 08/05/08 NXR Added Auto-A information.