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16-Mbit (1M x 16 / 2M x 8) Static RAM

CY62167E MoBL

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-15607 Rev. *A Revised June 07, 2007

Features

• Configurable as 1M x 16 or as 2M x 8 SRAM

• Very high speed: 45 ns

• Wide voltage range: 4.5V–5.5V

• Ultra low standby power

— Typical standby current: 1.5 µA

— Maximum standby current: 12 µA

• Ultra low active power

— Typical active current: 2.2 mA @ f = 1 MHz

• Easy memory expansion with CE

, CE

, and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

• Offered in 48-pin TSOP I package

Functional Description

[1]

The CY62167E is a high performance CMOS static RAM

organized as 1M words by 16 bits/2M words by 8 bits. This

device features advanced circuit design to provide an ultra low

active current. This is ideal for providing More Battery Life™

(MoBL

) in portable applications such as cellular telephones.

The device also has an automatic power down feature that

reduces power consumption by 99% when addresses are not

toggling. Place the device into standby mode when deselected

(CE

HIGH, or CE

LOW, or both BHE and BLE are HIGH).

The input and output pins (IO

through IO

) are placed in a

high impedance state when:

• The device is deselected (CE

HIGH or CE

LOW)

• Outputs are disabled (OE

HIGH)

• Both Byte High Enable and Byte Low Enable are disabled

(BHE

, BLE HIGH) or

• A write operation is in progress (CE

LOW, CE

HIGH, and

LOW)

To write to the device, take Chip Enables (CE

LOW and CE

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE

) is LOW, then data from IO pins (IO

through IO

), is

written into the location specified on the address pins (A

through A

). If Byte High Enable (BHE) is LOW, then data

from the IO pins (IO

through IO

) is written into the location

specified on the address pins (A

through A

To read from the device, take Chip Enables (CE

LOW and

HIGH) and Output Enable (OE) LOW while forcing the

Write Enable (WE

) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins appears on IO

to IO

. If Byte High Enable (BHE) is LOW,

then data from memory appears on IO

to IO

. See the “Truth

Table” on page 10 for a complete description of read and write

modes.

Logic Block Diagram

1M × 16 / 2M x 8

RAM ARRAY

–IO

ROW DECODER

COLUMN DECODER

SENSE AMPS

DATA IN DRIVERS

–IO

BLE

BHE

POWER DOWN

CIRCUIT

BHE

BLE

BYTE

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

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Summary of content (12 pages)

PAGE 1
CY62167E MoBL® 16-Mbit (1M x 16 / 2M x 8) Static RAM Features • • • • (CE1 HIGH, or CE2 LOW, or both BHE and BLE are HIGH).
PAGE 2
CY62167E MoBL® Pin Configuration[2, 3] 48-Pin TSOP I Top View A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 NC BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss IO15/A20 IO7 IO14 IO6 IO13 IO5 IO12 IO4 Vcc IO11 IO3 IO10 IO2 IO9 IO1 IO8 IO0 OE Vss CE1 A0 Product Portfolio Power Dissipation Product Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62167ELL Min Ty
PAGE 3
CY62167E MoBL® DC Input Voltage[5, 6] ........................................–0.5V to 6.0V Maximum Ratings Exceeding the maximum ratings may shorten the battery life of the device. User guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................ –55°C to + 125°C Supply Voltage to Ground Potential ........................................................... –0.5V to 6.
PAGE 4
CY62167E MoBL® AC Test Loads and Waveforms R1 VCC OUTPUT VCC GND 30 pF R2 10% ALL INPUT PULSES 90% 90% 10% FALL TIME= 1 V/ns RISE TIME= 1 V/ns INCLUDING JIG AND SCOPE EQUIVALENT TO: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters Values Unit R1 1800 Ω R2 990 Ω RTH 639 Ω VTH 1.
PAGE 5
CY62167E MoBL® Switching Characteristics Over the Operating Range[13, 14] Parameter Description 45 ns Min Max Unit READ CYCLE tRC Read Cycle Time 45 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns tDOE OE LOW to Data Valid 22 ns 45 LOW-Z[15] tLZOE OE LOW to tHZOE OE HIGH to High-Z[15, 16] ns 10 ns ns 5 ns 18 ns CE1 LOW and CE2 HIGH to Low-Z[15] tHZCE CE1 HIGH and CE2 LOW to High-Z[15, 16] tPU CE1 LOW and CE2 HIG
PAGE 6
CY62167E MoBL® Switching Waveforms Figure 1 shows address transition controlled read cycle waveforms.[18, 19] Figure 1. Read Cycle No. 1 tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 2 shows OE controlled read cycle waveforms.[19, 20] Figure 2. Read Cycle No. 2 ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 18.
PAGE 7
CY62167E MoBL® Switching Waveforms (continued) Figure 3 shows WE controlled write cycle waveforms.[17, 21, 22] Figure 3. Write Cycle No. 1 tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA IO NOTE 23 VALID DATA tHZOE Notes 21. Data IO is high impedance if OE = VIH. 22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 23. During this period the IOs are in output state and input signals must not be applied.
PAGE 8
CY62167E MoBL® Switching Waveforms (continued) Figure 4 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22] Figure 4. Write Cycle No. 2 tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE DATA IO tHD tSD NOTE 23 VALID DATA tHZOE Figure 5 shows WE controlled, OE LOW write cycle waveforms.[22] Figure 5. Write Cycle No. 3 tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATA IO NOTE 23 VALID DATA tHZWE Document #: 001-15607 Rev.
PAGE 9
CY62167E MoBL® Switching Waveforms (continued) Figure 6 shows BHE/BLE controlled, OE LOW write cycle waveforms.[22] Figure 6. Write Cycle No. 4 tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA IO NOTE 23 Document #: 001-15607 Rev.
PAGE 10
CY62167E MoBL® Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X X X X X L H H L H L Inputs Outputs Mode Power High-Z Deselect/Power Down Standby (ISB) X High-Z Deselect/Power Down Standby (ISB) H H High-Z Deselect/Power Down Standby (ISB) L L L Data Out (IO0–IO15) Read Active (ICC) H L H L Data Out (IO0–IO7); High-Z (IO8–IO15) Read Active (ICC) H H L L H High-Z (IO0–IO7); Data Out (IO8–IO15) Read Active (ICC) L H H H L H High-Z Out
PAGE 11
CY62167E MoBL® Package Diagram Figure 7. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183 DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] N 1 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.002[0.05] 0.006[0.15] 0.724 [18.40] 0.047[1.20] MAX. SEATING PLANE 0.004[0.10] 0.787[20.00] 0.004[0.10] 0.008[0.21] 0.010[0.25] GAUGE PLANE 0°-5° 0.020[0.50] 0.028[0.70] Document #: 001-15607 Rev. *A 51-85183-*A Page 11 of 12 © Cypress Semiconductor Corporation, 2007.
PAGE 12
CY62167E MoBL® Document History Page Document Title: CY62167E MoBL® 16-Mbit (1M x 16 / 2M x 8) Static RAM Document Number: 001-15607 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 1103145 See ECN VKN New Data Sheet *A 1138903 See ECN VKN Converted from preliminary to final Changed ICC(max) spec from 2.8 mA to 4.