Low Skew Clock Buffer Specification Sheet

CY7B9910
CY7B9920
Document Number: 38-07135 Rev. *B Page 5 of 11
AC Test Loads and Waveforms
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz, V
CC
= 5.0V 10 pF
7B9910–3
7B9910–4
TTL AC Test Load (CY7B9910) TTL Input Test Waveform (Cy7B9910)
5V
R1
R2
C
L
R1
R2
C
L
7B9910–5
CMOS AC Test Load (CY7B9920)
3.0V
2.0V
V
th
=1.5V
0.8V
0.0V
≤1ns
≤1ns
2.0V
0.8V
V
th
=1.5V
80%
V
th
=V
CC
/2
20%
0.0V
≤ 3ns
≤ 3ns
80%
20%
V
th
=V
CC
/2
7B9910–6
CMOS Input Test Waveform (CY7B9920)
V
CC
R1=130
R2=91
C
L
=50pF(C
L
= 30pF for –5 and – 2 devices)
(Includes fixture and probe capacitance)
R1=100
R2=100
C
L
=50pF(C
L
=30 pF for –5 and – 2devices)
(Includes fixture and probe capacitance)
V
CC
Switching Characteristics
Over the Operating Range
[11]
CY7B9910–2
[8]
CY7B9920–2
[8]
Parameter Description Min Typ Max Min Typ Max Unit
f
NOM
Operating Clock
Frequency in MHz
FS = LOW
[1, 2]
15 30 15 30 MHz
FS = MID
[1, 2]
25 50 25 50
FS = HIGH
[1, 2, 3]
40 80 40 80
[12]
t
RPWH
REF Pulse Width HIGH 5.0 5.0 ns
t
RPWL
REF Pulse Width LOW 5.0 5.0 ns
t
SKEW
Zero Output Skew (All Outputs)
[13, 14]
0.1 0.25 0.1 0.25 ns
t
DEV
Device-to-Device Skew
[14, 15]
0.75 0.75 ns
t
PD
Propagation Delay, REF Rise to FB Rise –0.25 0.0 +0.25 –0.25 0.0 +0.25 ns
t
ODCV
Output Duty Cycle Variation
[16]
–0.65 0.0 +0.65 –0.65 0.0 +0.65 ns
t
ORISE
Output Rise Time
[17, 18]
0.15 1.0 1.2 0.5 2.0 2.5 ns
t
OFALL
Output Fall Time
[17, 18]
0.15 1.0 1.2 0.5 2.0 2.5 ns
t
LOCK
PLL Lock Time
[19]
0.5 0.5 ms
t
JR
Cycle-to-Cycle Output Jitter Peak to Peak 200 200 ps
RMS 25 25 ps
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