High Speed Low Voltage Programmable Skew Clock Buffer Specification Sheet

ManualsBrandsCypress ManualsClockCY7B9911V

CY7B9911V

3.3V RoboClock+™

High Speed Low Voltage Programmable Skew

Clock Buffer

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-07408 Rev. *D Revised June 20, 2007

Features

■ All output pair skew <100 ps typical (250 max)

■ 3.75 to 110 MHz output operation

■ User selectable output functions

❐ Selectable skew to 18 ns

❐ Inverted and non-inverted

❐ Operation at

⁄

and

⁄

input frequency

❐ Operation at 2x and 4x input frequency (input as low as

3.75 MHz)

■ Zero input-to-output delay

■ 50% duty cycle outputs

■ LVTTL outputs drive 50Ω terminated lines

■ Operates from a single 3.3V supply

■ Low operating current

■ 32-pin PLCC package

■ Jitter 100 ps (typical)

Functional Description

The CY7B9911V 3.3V RoboClock+™ High Speed Low

Voltage Programmable Skew Clock Buffer (LVPSCB) offers

user selectable control over system clock functions. These

multiple output clock drivers provide the system integrator with

functions necessary to optimize the timing of high perfor-

mance computer systems. Each of the eight individual drivers,

arranged in four pairs of user controllable outputs, can drive

terminated transmission lines with impedances as low as 50Ω.

They deliver minimal and specified output skews and full swing logic

levels (LVTTL).

Each output is hardwired to one of nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are deter-

mined by the operating frequency with outputs that can skew

up to ±6 time units from their nominal “zero” skew position. The

completely integrated PLL allows external load and cancels

the transmission line delay effects. When this “zero delay”

capability of the LVPSCB is combined with the selectable

output skew functions, you can create output-to-output delays

of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

allow distribution of a low frequency clock that are multiplied

by two or four at the clock destination. This facility minimizes

clock distribution difficulty enabling maximum system clock

speed and flexibility.

TEST

REF

VCO AND

TIME UNIT

GENERATOR

SELECT

INPUTS

(THREE

LEVEL)

SKEW

SELECT

MATRIX

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

FILTER

PHASE

FREQ

DET

Logic Block Diagram

[+] Feedback

Summary of content (14 pages)

PAGE 1
CY7B9911V 3.3V RoboClock+™ High Speed Low Voltage Programmable Skew Clock Buffer Features Functional Description ■ All output pair skew <100 ps typical (250 max) ■ 3.75 to 110 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns ❐ Inverted and non-inverted 1 1 ❐ Operation at ⁄2 and ⁄4 input frequency ❐ Operation at 2x and 4x input frequency (input as low as 3.75 MHz) The CY7B9911V 3.
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CY7B9911V 3.3V RoboClock+™ Pin Configuration FS VCCQ REF GND 4 3 2 1 32 31 30 29 2F1 3F0 TEST PLCC 2F0 3F1 5 4F0 6 28 GND 4F1 7 27 1F1 VCCQ 8 26 1F0 VCCN 9 25 VCCN 4Q1 10 24 1Q0 4Q0 11 23 1Q1 GND 12 22 GND GND 13 21 14 15 16 17 18 19 20 GND 2Q0 2Q1 VCCN FB VCCN 3Q0 3Q1 CY7B9911V Pin Definitions IO Description REF Signal Name I Reference frequency input.
PAGE 3
CY7B9911V 3.3V RoboClock+™ Block Diagram Description Skew Select Matrix The Phase Frequency Detector and Filter blocks accept inputs from the Reference Frequency (REF) input and the Feedback (FB) input. They generate correction information to control the frequency of the Voltage Controlled Oscillator (VCO). These blocks, along with the VCO, form a Phase Locked Loop (PLL) that tracks the incoming REF signal. The skew select matrix is comprised of four independent sections.
PAGE 4
CY7B9911V 3.3V RoboClock+™ Figure 1 shows the typical outputs with FB connected to a zero skew output.[4] U U U U U U t 0 +1t t 0 +2t t 0 +3t t 0 +4t t 0 +5t t 0 +6t t0 t 0 – 1t U t 0 – 2t U t 0 – 3t U t 0 – 4t U t 0 – 5t U t 0 – 6t U Figure 1.
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CY7B9911V 3.3V RoboClock+™ Operational Mode Descriptions Figure 2. Zero Skew and Zero Delay Clock Driver REF LOAD Z0 L1 SYSTEM CLOCK FB REF FS LOAD 4F0 4F1 4Q0 4Q1 3F0 3F1 3Q0 3Q1 2F0 2F1 2Q0 2Q1 1F0 1F1 1Q0 1Q1 L2 Z0 LOAD L3 Z0 L4 LOAD TEST Z0 LENGTH L1 = L2 = L3 = L4 Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode the CY7B9911V is used as the basis for a low skew clock distribution tree.
PAGE 6
CY7B9911V 3.3V RoboClock+™ groups, and the PLL aligns the rising edges of REF and FB, you can create wider output skews by proper selection of the xFn inputs. For example, a +10 tU between REF and 3Qx is achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx skews to +6 tU, a total of +10 tU skew is realized). Many other configurations are realized by skewing both the outputs used as the FB input and skewing the other outputs. Figure 4.
PAGE 7
CY7B9911V 3.3V RoboClock+™ frequency, while still maintaining the low skew characteristics of and four or divide by two (and four) at the same time. This shifts the clock driver. The LVPSCB performs all of the functions its outputs over a wide range or maintain zero skew between described in this section at the same time. It can multiply by two selected outputs. Figure 7. Multi-Function Clock Driver REF LOAD Z0 110 MHz INVERTED FB REF FS 27.
PAGE 8
CY7B9911V 3.3V RoboClock+™ Maximum Ratings Output Current into Outputs (LOW)............................. 64 mA Operating outside these boundaries may affect the performance and life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage to Ground Potential................–0.5V to +7.0V Static Discharge Voltage.............
PAGE 9
CY7B9911V 3.3V RoboClock+™ Capacitance Tested initially and after any design or process changes that may affect these parameters.[10] Parameter CIN Description Test Conditions Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V Max Unit 10 pF Note 10. Applies to REF and FB inputs only. AC Test Loads and Waveforms Figure 9. AC Test Loads and Waveforms VCC R1 CL R2 3.0V 2.0V Vth =1.5V 0.8V 0.0V R1=100 R2=100 CL = 30 pF (Includes fixture and probe capacitance) 2.0V Vth =1.5V 0.
PAGE 10
CY7B9911V 3.3V RoboClock+™ Switching Characteristics – 7 Option Over the Operating Range[2, 11] Parameter fNOM CY7B9911V-7 Description Operating Clock Frequency in MHz Min Typ Max FS = LOW[1, 2] 15 30 FS = MID[1, 2] 25 50 40 110 FS = HIGH[1, 2 , 3] Unit MHz tRPWH REF Pulse Width HIGH 5.0 tRPWL REF Pulse Width LOW 5.0 tU Programmable Skew Unit tSKEWPR Zero Output Matched Pair Skew (XQ0, XQ1)[13, 14] 0.1 0.25 ns tSKEW0 Zero Output Skew (All Outputs)[13, 15] 0.3 0.75 ns 0.
PAGE 11
CY7B9911V 3.3V RoboClock+™ AC Timing Diagrams tREF tRPWL tRPWH REF tODCV tPD tODCV FB tJR Q tSKEWPR, tSKEW0,1 tSKEWPR, tSKEW0,1 OTHER Q tSKEW2 tSKEW2 INVERTED Q tSKEW3,4 tSKEW3,4 tSKEW3,4 REF DIVIDED BY 2 tSKEW1,3, 4 tSKEW2,4 REF DIVIDED BY 4 Document Number: 38-07408 Rev.
PAGE 12
CY7B9911V 3.
PAGE 13
CY7B9911V 3.3V RoboClock+™ Package Diagram Figure 10. 32-Pin Plastic Leaded Chip Carrier J65 51-85002-*B Document Number: 38-07408 Rev.
PAGE 14
CY7B9911V 3.3V RoboClock+™ Document History Page Document Title: CY7B9911V 3.3V RoboClock+™ High Speed Low Voltage Programmable Skew Clock Buffer Document Number: 38-07408 REV. ECN NO. Issue Date Orig.