Low Skew Clock Buffer Specification Sheet

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CY7B9910

CY7B9920

Low Skew Clock Buffer

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-07135 Rev. *B Revised August 07, 2007

Features

■ All outputs skew <100 ps typical (250 max.)

■ 15 to 80 MHz output operation

■ Zero input to output delay

■ 50% duty cycle outputs

■ Outputs drive 50Ω terminated lines

■ Low operating current

■ 24-pin SOIC package

■ Jitter:<200 ps peak to peak, <25 ps RMS

Functional Description

The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer

low skew system clock distribution. These multiple output clock

drivers optimize the timing of high performance computer

systems. Each of the eight individual drivers can drive terminated

transmission lines with impedances as low as 50Ω. They deliver

minimal and specified output skews and full swing logic levels

(CY7B9910 TTL or CY7B9920 CMOS).

The completely integrated PLL enables “zero delay” capability.

External divide capability, combined with the internal PLL, allows

distribution of a low frequency clock that is multiplied by virtually

any factor at the clock destination. This facility minimizes clock

distribution difficulty while allowing maximum system clock

speed and flexibility.

Block Diagram Description

Phase Frequency Detector and Filter

The Phase Frequency Detector and Filter blocks accept inputs

from the reference frequency (REF) input and the feedback (FB)

input and generate correction information to control the

frequency of the Voltage Controlled Oscillator (VCO). These

blocks, along with the VCO, form a Phase Locked Loop (PLL)

that tracks the incoming REF signal.

VCO

The VCO accepts analog control inputs from the PLL filter block

and generates a frequency. The operational range of the VCO is

determined by the FS control pin.

TEST

REF

VOLTAGE

CONTROLLED

OSCILLATOR

FILTER

PHASE

FREQ

DET

Logic Block Diagram

[+] Feedback [+] Feedback

Summary of content (11 pages)

PAGE 1
CY7B9910 CY7B9920 Low Skew Clock Buffer Features ■ All outputs skew <100 ps typical (250 max.) ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows distribution of a low frequency clock that is multiplied by virtually any factor at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.
PAGE 2
CY7B9910 CY7B9920 Pin Configuration SOIC Top View REF VCCQ FS NC VCCQ VCCN Q0 Q1 GND Q2 Q3 VCCN 1 24 2 23 3 22 4 21 20 5 6 7 7B9910 7B9920 19 18 8 17 9 16 10 15 11 14 12 13 GND TEST NC GND VCCN Q7 Q6 GND Q5 Q4 VCCN FB Pin Definitions Signal Name IO Description REF I Reference frequency input.This input supplies the frequency and timing against which all functional variations are measured. FB I PLL feedback input (typically connected to one of the eight outputs).
PAGE 3
CY7B9910 CY7B9920 Maximum Ratings Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Operating outside these boundaries may affect the performance and life of the device. These user guidelines are not tested. Latch Up Current ..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied ........................................
PAGE 4
CY7B9910 CY7B9920 Electrical Characteristics Over the Operating Range CY7B9910 Parameter VOH Description Test Conditions Min Output HIGH Voltage VCC = Min, IOH = –16 mA 2.4 Max Output LOW Voltage Max Unit V VCC = Min, IOH =–40 mA VOL CY7B9920 Min VCC –0.75 VCC = Min, IOL = 46 mA 0.45 V VCC = Min, IOL = 46 mA 0.45 VIH Input HIGH Voltage (REF and FB inputs only) 2.0 VCC VCC – 1.35 VCC V VIL Input LOW Voltage (REF and FB inputs only) –0.5 0.8 –0.5 1.
PAGE 5
CY7B9910 CY7B9920 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions CIN Max Unit 10 pF TA = 25°C, f = 1 MHz, VCC = 5.0V Input Capacitance AC Test Loads and Waveforms 5V R1 CL R2 3.0V 2.0V Vth =1.5V 0.8V 0.0V R1=130 R2=91 CL = 50 pF (CL = 30pF for –5 and – 2 devices) (Includes fixture and probe capacitance) 2.0V Vth =1.5V 0.
PAGE 6
CY7B9910 CY7B9920 CY7B9910–5 Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW Min [1, 2] Min Typ Max 15 30 15 30 25 50 25 50 FS = HIGH[1, 2, 3] 40 80 40 80[12] REF Pulse Width HIGH 5.0 tRPWL REF Pulse Width LOW 5.0 tSKEW Zero Output Skew (All Outputs)[13, 14] 5.0 tDEV Device-to-Device tPD Propagation Delay, REF Rise to FB Rise 0.5 MHz ns 0.25 1.0 Variation[16] Unit ns 5.0 0.
PAGE 7
CY7B9910 CY7B9920 Switching Characteristics Over the Operating Range[11] (continued) CY7B9910–7 Parameter fNOM Description Operating Clock Frequency in MHz Min Typ CY7B9920–7 Max Min FS = LOW[1, 2] 15 30 15 Typ Max Unit 30 MHz FS = MID[1, 2] 25 50 25 50 FS = HIGH1, 2, 3] 40 80 40 80[12] tRPWH REF Pulse Width HIGH 5.0 5.0 ns tRPWL REF Pulse Width LOW 5.0 5.
PAGE 8
CY7B9910 CY7B9920 AC Timing Diagrams Figure 1. AC Timing Diagrams tREF tRPWL tRPWH REF tPD tODCV tODCV FB Q tJR tSKEW tSKEW OTHER Q Figure 2. Zero Skew and Zero Delay Clock Driver REF LOAD Z0 SYSTEM CLOCK FB REF FS LOAD Q0 Q1 Z0 Q2 Q3 Q4 Q5 LOAD Z0 Q6 Q7 LOAD TEST Z0 Document Number: 38-07135 Rev.
PAGE 9
CY7B9910 CY7B9920 Operational Mode Descriptions Figure 2 shows the device configured as a zero skew clock buffer. In this mode the 7B9910/9920 is used as the basis for a low skew clock distribution tree. The outputs are aligned and may each drive a terminated transmission line to an independent load. The FB input is tied to any output and the operating frequency range is selected with the FS pin.
PAGE 10
CY7B9910 CY7B9920 Ordering Information Accuracy (ps) 250 500 750 Pb-Free 250 500 750 CY7B9910–2SC CY7B9910–2SCT CY7B9920–2SC[20] CY7B9910–5SC CY7B9910–5SCT CY7B9910–5SI CY7B9910–5SIT CY7B9920–5SC CY7B9920–5SCT CY7B9920–5SI CY7B9910–7SC CY7B9910–7SI[20] CY7B9920–7SC[20] CY7B9920–7SI[20] 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Small Outline IC 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Smal
PAGE 11
CY7B9910 CY7B9920 Document History Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer Document Number: 38-07135 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110244 10/28/01 SZV Change from Specification number: 38-00437 to 38-07135 *A 1199925 See ECN DPF/AESA Added Pb-free parts in Ordering Information Added Note 20: Not recommended for the new design *B 1353343 See ECN AESA Change status to final © Cypress Semiconductor Corporation, 2001-2007.