Dual-Port Static RAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C038V

CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

3.3V 32K/64K x 16/18 Dual-Port Static

RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 38-06078 Rev. *B Revised December 09, 2008

Features

■

True Dual-Ported memory cells which allow

simultaneous access of the same memory location

■

32K x 16 organization (CY7C027V/027VN/027AV

[1]

)

■

64K x 16 organization (CY7C028V)

■

32K x 18 organization (CY7C037V/037AV

[2]

)

■

64K x 18 organization (CY7C038V)

■

0.35 micron CMOS for optimum speed and power

■

High speed access: 15, 20, and 25 ns

■

Low operating power

■

Active: I

= 115 mA (typical)

■

Standby: I

SB3

= 10 μA (typical)

■

Fully asynchronous operation

■

Automatic power down

■

Expandable data bus to 32/36 bits or more using Master/Slave

chip select when using more than one device

■

On-chip arbitration logic

■

Semaphores included to permit software handshaking

between ports

■

INT flag for port-to-port communication

■

Separate upper-byte and lower-byte control

■

Dual chip enables

■

Pin select for Master or Slave

■

Commercial and Industrial temperature ranges

■

100-pin Pb-free TQFP and 100-pin TQFP

Notes

1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical.

2. CY7C037V and CY7C037AV are functionally identical.

3. I/O

–I/O

for x16 devices; I/O

–I/O

for x18 devices.

4. I/O

–I/O

for x16 devices; I/O

–I/O

for x18 devices.

5. A

–A

for 32K; A

–A

for 64K devices.

6. BUSY

is an output in master mode and an input in slave mode.

R/W

I/O

8/9L

–I/O

15/17L

I/O

Control

Address

Decode

–A

14/15L

R/W

BUSY

I/O

Control

Interrupt

Semaphore

Arbitration

SEM

INT

M/S

I/O

–I/O

7/8L

R/W

I/O

8/9L

–I/O

15/17R

I/O

–I/O

7/8R

Logic Block Diagram

–A

14/15L

True Dual-Ported

RAM Array

–A

14/15R

R/W

BUSY

SEM

INT

Address

Decode

–A

14/15R

[3]

[4]

[5]

[6]

[5] [5]

15/16

8/9

15/16

8/9

15/16 15/16

[+] Feedback

Summary of content (18 pages)

PAGE 1
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V 3.3V 32K/64K x 16/18 Dual-Port Static RAM Features ■ ■ ■ True Dual-Ported memory cells which allow simultaneous access of the same memory location [1] ■ 32K x 16 organization (CY7C027V/027VN/027AV ) ■ 64K x 16 organization (CY7C028V) [2] ■ 32K x 18 organization (CY7C037V/037AV ) ■ 64K x 18 organization (CY7C038V) ■ 0.
PAGE 2
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Pin Configurations A8R A7R A6R A5R A4R A3R A2R A1R A0R INTR BUSYR M/S GND BUSYL INTL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L Figure 1.
PAGE 3
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Pin Configurations (continued) A7R A6R A5R A4R A3R A2R A1R A0R INTR BUSYR M/S VCC GND GND BUSYL INTL A0L A1L A2L A3L A4L A5L A6L A7L A8L Figure 2.
PAGE 4
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Pin Definitions Left Port Right Port Description CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH) R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A15L A0R–A15R Address (A0–A14 for 32K; A0–A15 for 64K devices) I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices; I/O0–I/O17 for x18) SEML SEMR Semaphore Enable UBL UBR Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 dev
PAGE 5
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it.
PAGE 6
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V DC Input Voltage[2] .................................. –0.5V to VCC+0.5V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 1100V Storage Temperature ................................. –65°C to +150°C Latch-up Current..........................................
PAGE 7
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Figure 3. AC Test Loads and Waveforms 3.3V 3.3V R1 = 590Ω C = 30 pF RTH = 250Ω OUTPUT OUTPUT R1 = 590Ω OUTPUT C = 30 pF R2 = 435Ω C = 5 pF R2 = 435Ω VTH = 1.4V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.
PAGE 8
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Characteristics Over the Operating Range[6](continued) CY7C027V/027VN/027AV/028V/ CY7C037V/037AV/038V Parameter Description -15 Min -20 Max 0 Min Unit -25 Max Min 0 Max tHD Data Hold From Write End tHZWE[9, 10] R/W LOW to High Z 0 tLZWE[9 ,10] R/W HIGH to Low Z tWDD[36] tDDD[36] Write Pulse to Data Delay 30 40 50 ns Write Data Valid to Read Data Valid 25 30 35 ns tBLA BUSY LOW from Address Match 15 20 20 ns tBHA BUS
PAGE 9
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access)[15, 16, 17] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[15, 18, 19] tACE CE and LB or UB tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Figure 6. Read Cycle No.
PAGE 10
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) Figure 7. Write Cycle No. 1: R/W Controlled Timing[20, 21, 22, 23] tWC ADDRESS tHZOE [26] OE tAW CE [24,25] tPWE[23] tSA tHA R/W tHZWE[26] DATA OUT tLZWE NOTE 27 NOTE 27 tSD tHD DATA IN Figure 8. Write Cycle No. 2: CE Controlled Timing[20, 21, 22, 28] tWC ADDRESS tAW CE [24,25] tSA tSCE tHA R/W tSD tHD DATA IN Notes 20. R/W must be HIGH during all address transitions. 21.
PAGE 11
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) Figure 9. Semaphore Read After Write Timing, Either Side[29] tSAA A0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O 0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Figure 10. Timing Diagram of Semaphore Contention[30, 31, 32] A0L –A2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes 29.
PAGE 12
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)[33] tWC ADDRESSR MATCH tPWE R/WR tSD DATA INR tHD VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Figure 12. Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note 33. CEL = CER = LOW. Document #: 38-06078 Rev.
PAGE 13
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)[34] CELValid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Figure 14. Busy Timing Diagram No.
PAGE 14
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) Figure 15.
PAGE 15
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Table 1.
PAGE 16
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Ordering Information 32K x16 3.
PAGE 17
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-*C Document #: 38-06078 Rev.
PAGE 18
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document History Page Document Title: CY7C027V/027VN/027AV/CY7C028V/037V/037AV/038V 3.3V 32K/64K x 16/18 Dual Port Static RAM Document Number: 38-06078 Rev. ECN No. Orig. of Change Submission Date ** 237626 YDT 6/30/04 *A 259110 JHX See ECN Added Pb-Free packaging information.