CY7C0430BV CY7C0430CV 10 Gb/s 3.3V QuadPort™ DSE Family Features • Dual Chip Enables on all ports for easy depth expansion • QuadPort™ datapath switching element (DSE) family allows four independent ports of access for data path management and switching • High-bandwidth data throughput up to 10 Gb/s • 133-MHz[1] port speed x 18-bit-wide interface × 4 ports • High-speed clock to data access 4.2 ns (max.
CY7C0430BV CY7C0430CV PORT 1 PORT 2 PORT 4 PORT 3 DATA PATH AGGREGATOR Processor 1 Pre-processed DATA Path QuadPort DSE Family Processed DATA Path Processor 2 DATA PATH MANAGER FOR PARALLEL PACKET PROCESSING Queue #1 PORT 1 PORT 3 Queue #2 PORT 2 PORT 4 DATA CLASSIFICATION ENGINE Functional Description The Quadport Datapath Switching Element (DSE) family offers four ports that may be clocked at independent frequencies from one another.
CY7C0430BV CY7C0430CV counter is loaded with an external address when the port’s Counter Load pin (CNTLD) is asserted LOW. When the port’s Counter Increment pin (CNTINC) is asserted, the address counter will increment on each subsequent LOW-to- HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTINC is deasserted. The counter can address the entire switch array and will loop back to the start.
CY7C0430BV CY7C0430CV Port 1 Operation-Control Logic Block Diagram (Address Readback is independent of CEs) R/WP1 W UBP1 CE0P1 CE1P1 LBP1 OEP1 I/O9P1–I/O17P1 I/O0P1–I/O8P1 9 Port-1 I/O Control 9 Addr. Read Port 1 Readback Register MRST 16 t1 rt MKLDP1 Decision Logic CLKP1 MRST CNTINTP1 Document #: 38-06027 Rev.
CY7C0430BV CY7C0430CV Pin Configuration 272-ball Grid Array (BGA) Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A LB P1 I/O17 P2 I/O15 P2 I/O13 P2 I/O11 P2 I/O9 P2 I/O16 P1 I/O14 P1 I/O12 P1 I/O10 P1 I/O10 P4 I/O12 P4 I/O14 P4 I/O16 P4 I/O9 P3 I/O11 P3 I/O13 P3 I/O15 P3 I/O17 P3 LB P4 B VDD1 UB P1 I/O16 P2 I/O14 P2 I/O12 P2 I/O10 P2 I/O17 P1 I/O13 P1 I/O11 P1 TMS TDI I/O11 P4 I/O13 P4 I/O17 P4 I/O10 P3 I/O12 P3 I/O14 P3 I/O16 P3 UB P
CY7C0430BV CY7C0430CV Selection Guide fMAX2 CY7C0430CV –133 CY7C0430CV –100 Unit 133[1] 100 MHz Max Access Time (Clock to Data) 4.2 5.0 ns Max Operating Current ICC 750 600 mA Max Standby Current for ISB1 (All ports TTL Level) 200 150 mA Max Standby Current for ISB3 (All ports CMOS Level) 15 15 mA Pin Definitions Port 1 Port 2 Port 3 Port 4 Description A0P1–A15P1 A0P2–A15P2 A0P3–A15P3 A0P4–A15P4 Address Input/Output.
CY7C0430BV CY7C0430CV Pin Definitions (continued) Port 1 Port 2 Port 3 Port 4 Description CNTRDP1 CNTRDP2 CNTRDP3 CNTRDP4 Counter Readback Input. When asserted LOW, the internal address value of the counter will be read back on the address lines. During CNTRD operation, both CNTLD and CNTINC must be HIGH. Counter readback operation has higher priority over mask register readback operation. Counter readback operation is independent of port chip enables.
CY7C0430BV CY7C0430CV Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................–55°C to + 125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2200V Latch-up Current.....................................................
CY7C0430BV CY7C0430CV AC Test Load Z0 = 50Ω OUTPUT R = 50Ω OUTPUT C [5] Z0 = 50Ω R = 50Ω 5 pF VTH = 1.5V VTH = 1.5V (a) Normal Load OUTPUT Z0 = 50Ω R = 50Ω 5 pF VTH = 3.3V 1.5V (b) Three-State Delay 50Ω TDO Z0 =50Ω C = 10 pF 3.0V GND GND (c) TAP Load 10% 90% 90% 10% tF tR All Input Pulses Note: 5. Test conditions: C = 10 pF. Document #: 38-06027 Rev.
CY7C0430BV CY7C0430CV Switching Characteristics Over the Industrial Operating Range [6] CY7C0430BV and CY7C0430CV –133 Parameter Description Min. –100 Max. Min. Max. Unit 100 MHz fMAX2[7] tCYC2[7] Maximum Frequency Clock Cycle Time 7.5 10 ns tCH2 Clock HIGH Time 3 4 ns tCL2 Clock LOW Time 3 tR Clock Rise Time 2 3 ns tF Clock Fall Time 2 3 ns tSA Address Set-up Time 2.3 3 ns tHA Address Hold Time 0.7 0.7 ns tSC Chip Enable Set-up Time 2.
CY7C0430BV CY7C0430CV Switching Characteristics Over the Industrial Operating Range (continued)[6] CY7C0430BV and CY7C0430CV –133 Parameter Description Min. –100 Max. Min. Max. Unit tCKLZ[9] Clock HIGH to Output Low-Z 1 tSINT Clock to INT Set Time 1 7.5 tRINT Clock to INT Reset Time 1 7.5 1 10 ns tSCINT Clock to CNTINT Set Time 1 7.5 1 10 ns tRCINT Clock to CNTINT Reset Time 1 7.5 1 10 ns 1 ns 1 10 ns Master Reset Timing tRS Master Reset Pulse Width 7.
CY7C0430BV CY7C0430CV tTH tTL Test Clock TCK tTCYC tTMSH tTMSS Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOX tTDOV Switching Waveforms Master Reset[10] tCH2 tCYC2 tCL2 CLK tRS MRST ALL ADDRESS/ DATA LINES tRSF ALL OTHER INPUTS tRSR INACTIVE tS ACTIVE TMS[11] CNTINT INT TDO Notes: 10. tS is the set-up time required for all input control signals. 11. To Reset the test port without resetting the device, TMS must be held low for five clock cycles.
CY7C0430BV CY7C0430CV Switching Waveforms (continued) Read Cycle[12, 13, 14, 15, 16] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSB tHB tSW tSA tHW tHA tSC tHC LB UB R/W ADDRESS An DATAOUT An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes: 12. OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge. 13. CNTLD = VIL, MKLD = VIH, CNTINC = x, and MRST = CNTRST = VIH. 14.
CY7C0430BV CY7C0430CV Switching Waveforms (continued) Bank Select Read[17, 18] tCH2 tCYC2 tCL2 CLK tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE(B1) tCD2 tHC tSC tCD2 tHA tSA A0 ADDRESS(B2) tDC A1 tCKHZ Q3 Q1 Q0 DATAOUT(B1) tCD2 tCKHZ tDC tCKLZ A3 A2 A4 A5 tHC tSC CE(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 Q4 Q2 tCKLZ tCKLZ Read-to-Write-to-Read (OE = VIL)[19, 20, 21, 22] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W tSW tHW An ADDRESS tSA An+1 An+2 An+
CY7C0430BV CY7C0430CV Switching Waveforms (continued) Read-to-Write-to-Read (OE Controlled)[19, 20, 21, 22] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W ADDRESS tSW tHW An tSA An+1 An+2 tHA An+3 An+4 An+5 tSD tHD Dn+2 DATAIN Dn+3 tCD2 tCD2 DATAOUT Qn Qn+4 tOHZ tCKLZ OE Read Write Read Read with Address Counter Advance[23, 24] tCH2 tCYC2 tCL2 CLK tSA ADDRESS tHA An tSCLD tHCLD CNTLD tSCINC tHCINC CNTINC tCD2 DATAOUT Qx–1 Qx Read External Address tDC Qn Read with Counte
CY7C0430BV CY7C0430CV Switching Waveforms (continued) Write with Address Counter Advance [24, 25] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSCLD tHCLD tSCINC tHCINC An+1 An+2 An+3 An+4 CNTLD CNTINC Dn DATAIN tSD tHD Write External Address Dn+1 Dn+1 Write with Counter Dn+2 Write Counter Hold Dn+3 Dn+4 Write with Counter Note: 25. CE0 = LB = UB = R/W = VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH. Document #: 38-06027 Rev.
CY7C0430BV CY7C0430CV Switching Waveforms (continued) Counter Reset [21, 26, 27] tCH2 tCYC2 tCL2 CLK tSA An ADDRESS INTERNAL ADDRESS tHA AX A0 tSW An+1 A1 An An+1 tHW R/W tHCLD tSCLD CNTLD CNTINC tSCRST An+2 tHCRST CNTRST tSD DATAIN tHD D0 DATAOUT Q0 Counter Reset Write Address 0 Read Address 0 Read Address 1 Q1 Qn Read Address n Notes: 26. CE0 = LB = UB = VIL; CE1 = MRST = MKLD = MKRD = CNTRD = VIH. 27. No dead cycle exists during counter reset.
CY7C0430BV CY7C0430CV Switching Waveforms (continued) Load and Read Address Counter[28] tCH2 tCYC2 tCL2 Note 29 CLK tHA tSA A0–A15 tCKLZ Note 30 tCA2 tCKHZ An+2[31] An tSCLD tHCLD CNTLD CNTINC tSCINC tHCINC tSCRD tHCRD CNTRD INTERNAL ADDRESS An An+1 Qx–1 Qx Load External Address An+2 tDC tCD2 DATAOUT An+2 Qn An+2 tCKHZ Qn+1 Read Data with Counter Qn+2 tCKLZ Qn+2 Read Internal Address Notes: 28. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = VIH. 29.
CY7C0430BV CY7C0430CV Switching Waveforms (continued) Load and Read Mask Register [32] tCH2 tCYC2 tCL2 Note 29 CLK tHA tSA A0–A15 tCKLZ Note 30 tCA2 tCKHZ An [33] An tSMLD tHMLD MKLD tSMRD tHMRD MKRD MASK INTERNAL VALUE An An An Load Mask Register Value An An Read Mask Register Value Notes: 32. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =VIH. 33. This is the value of the Mask Register read out on the address lines. Document #: 38-06027 Rev.
CY7C0430BV CY7C0430CV Switching Waveforms (continued) Port 1 Write to Port 2 Read[34, 35, 36] tCH2 tCYC2 tCL2 CLKP1 tHA tSA PORT-1 ADDRESS An tSW tHW R/WP1 tCKHZ tSD PORT-1 tCKLZ Dn DATAIN CLKP2 tHD tCYC2 tCL2 tCCS tCH2 PORT-2 ADDRESS tSA tHA An R/WP2 tCD2 PORT-2 Qn DATAOUT tDC Notes: 34. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =VIH. 35.
CY7C0430BV CY7C0430CV Switching Waveforms (continued) Counter Interrupt [37, 38, 39] tCH2 tCYC2 tCL2 CLK EXTERNAL ADDRESS 007Fh xx7Dh tSMLD tHMLD MKLD tSCLD tHCLD CNTLD tHCINC tSCINC CNTINC COUNTER INTERNAL ADDRESS xx7Dh An xx7Eh xx7Fh xx00h xx00h tSCINT CNTINT tRCINT Mailbox Interrupt Timing[40, 41, 42, 43, 44] tCH2 tCYC2 tCL2 CLKP1 tSA PORT-1 ADDRESS tHA An+1 An FFFE An+2 An+3 tSINT tRINT INTP2 tCH2 tCYC2 tCL2 CLKP2 tSA PORT-2 ADDRESS Am tHA Am+1 FFFE Am+3 Am+4 No
CY7C0430BV CY7C0430CV Table 1. Read/Write and Enable Operation (Any Port)[45, 46, 47] Inputs OE CLK Outputs Operation CE0 CE1 R/W I/O0–I/O17 X H X X High-Z Deselected X X L X High-Z Deselected X L H L DIN Write L L H H DOUT Read L H X High-Z Outputs Disabled H X Table 2.
CY7C0430BV CY7C0430CV Master Reset The QuadPort DSE device undergoes a complete reset by taking its Master Reset (MRST) input LOW. The Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked).
CY7C0430BV CY7C0430CV Address Counter Control Operations Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for the fast interleaved memory applications. A port’s burst counter is loaded with the port’s Counter Load pin (CNTLD). When the port’s Counter Increment (CNTINC) is asserted, the address counter will increment on each LOW to HIGH transition of that port’s clock signal.
CY7C0430BV CY7C0430CV Counter-Mask Register Example: Load Counter-Mask Register = 3F CNTINT H 0 0 0’s 215 214 H X X X’s 215 214 Max Address Register H X X L 1 1 1 X X 215 214 Mask Register bit-0 Counter Address X 0 0 1 0 0 0 26 25 24 23 22 21 20 X’s 215 214 Max + 1 Address Register 1 26 25 24 23 22 21 20 Blocked Address Load Address Counter = 8 0 1 1 X 1 1 1 1 1 1 Address Counter bit-0 26 25 24 23 22 21 20 X’s X 0 0 0 0 0 0 26 25 24 23 22 21 20 Figure 2.
CY7C0430BV CY7C0430CV address the entire memory array (depend on the value of the mask register) and loop back to location 0. The increment operation is second in priority to load operation. 3. Readback: the internal value of either the burst counter or the mask register can be read out on the address lines when CNTRD or MKRD is LOW. Counter readback has higher priority over mask register readback. A no-operation delay cycle is experienced when readback operation is performed.
CY7C0430BV CY7C0430CV The EXTEST, and SAMPLE/PRELOAD instructions can be used to capture the contents of the Input and Output ring. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the QuadPort DSE device and can be shifted out when the TAP controller is in the Shift-DR state.
CY7C0430BV CY7C0430CV number of TCK cycles depending on the TCK and CLKBIST frequency. t CYC [ CLKBIST ] t CYC = -------------------------------------------- × m + SPC t CYC [ TCK ] tCYC is total number of TCK cycles required to run MBIST. SPC is the Synchronization Padding Cycles (4–6 cycles). m is a constant represents the number of read and write operations required to run MBIST algorithms (31195136).
CY7C0430BV CY7C0430CV TAP Controller State Diagram (FSM)[53] 1 TEST-LOGIC RESET 0 0 RUN_TEST/ IDLE 1 1 SELECT DR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 1 0 1 SELECT IR-SCAN 0 UPDATE-IR 1 0 Note: 53. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-06027 Rev.
CY7C0430BV CY7C0430CV JTAG/BIST TAP Controller Block Diagram 0 Bypass Register (BYR) 1 0 MBIST Control Register (MCR) 3 2 1 0 Instruction Register (IR) 24 23 0 MBIST Result Register (MRR) TDI 31 30 29 TDO 0 Identification Register (IDR) 99 Selection Circuitry (MUX) 0 MBIST Debug Register (MDR) 391 0 Boundary Scan Register (BSR) BIST CONTROLLER TAP CONTROLLER CLKBIST TCK TMS MRST MEMORY CELL Table 4.
CY7C0430BV CY7C0430CV Table 5. Scan Registers Sizes Register Name Bit Size Instruction (IR) 4 Bypass (BYR) 1 Identification (IDR) 32 MBIST Control (MCR) 2 MBIST Result (MRR) 25 MBIST Debug (MDR) 100 Boundary Scan (BSR) 392 Table 6. Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input/Output ring contents. Places the boundary scan register (BSR) between the TDI and TDO. BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.
CY7C0430BV CY7C0430CV Table 7. MBIST Control States (continued) States Code State Name Description 001001 chkr_r All ports read topological checkerboard data. 001000 n_chkr_w Port 1 write inverse topological checkerboard data. 011000 n_chkr_r All ports read inverse topological checkerboard data. 011001 uaddr_zeros2 Port 2 write all zeros to memory using Unique Address Algorithm (UAA). 011011 uaddr_write2 Port 2 writes every address value into its memory location (UAA).
CY7C0430BV CY7C0430CV Table 9. Boundary Scan Order (continued) Table 9.
CY7C0430BV CY7C0430CV Table 9. Boundary Scan Order (continued) Cell # Signal Name Bump (Ball) ID Table 9.
CY7C0430BV CY7C0430CV Table 9.
CY7C0430BV CY7C0430CV Package Diagram 272-Lead PBGA (27 x 27 x 2.33 mm) BG272 51-85130-*A QuadPort is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06027 Rev. *B Page 36 of 37 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice.
CY7C0430BV CY7C0430CV Document History Page Document Title: CY7C0430BV, CY7C0430CV 10 Gb/s 3.3V QuadPort DSE Family Document Number: 38-06027 REV. ECN NO. Issue Date Orig.
