Synchronous Dual-Port Static RAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C09079V

CY7C09079V/89V/99V

CY7C09179V/89V/99V

3.3V 32K/64K/128K x 8/9

Synchronous Dual-Port Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-06043 Rev. *C Revised December 10, 2008

Features

■ True Dual-Ported memory cells which enable simultaneous

access of the same memory location

■ 6 Flow-Through and Pipelined devices

■ 32K x 8/9 organizations (CY7C09079V/179V)

■ 64K x 8/9 organizations (CY7C09089V/189V)

■ 128K x 8/9 organizations (CY7C09099V/199V)

■ 3 Modes

■ Flow-Through

■ Pipelined

■ Burst

■ Pipelined output mode on both ports enables fast 100 MHz

operation

■ 0.35-micron CMOS for optimum speed and power

■ High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.)

■ 3.3V low operating power

■ Active= 115 mA (typical)

■ Standby= 10 μA (typical)

■ Fully synchronous interface for easier operation

■ Burst counters increment addresses internally

■ Shorten cycle times

■ Minimize bus noise

■ Supported in Flow-Through and Pipelined modes

■ Dual Chip Enables for easy depth expansion

■ Automatic power down

■ Commercial and Industrial temperature ranges

■ Available in 100-pin TQFP

■ Pb-free packages available

Notes

1. See page 6 for Load Conditions.

2. I/O

–I/O

for x8 devices, I/O

–I/O

for x9 devices.

3. A

–A

for 32K, A

–A

for 64K, and A

–A

for 128K devices.

Logic Block Diagram

R/W

FT/Pipe

I/O

–I/O

7/8L

Control

–A

14/15/16L

CLK

ADS

CNTEN

CNTRST

R/W

0/1

FT/Pipe

I/O

–I/O

7/8R

I/O

Control

–A

14/15/16R

CLK

ADS

CNTEN

CNTRST

0/1

I/O

Counter/

Address

Decode

True Dual-Ported

RAM Array

Counter/

Address

Decode

8/9 8/9

[2]

[3]

15/16/17

CY7C0907 9V/89V/99V

CY7C0917 9V/89V/99V

[+] Feedback

Summary of content (21 pages)

PAGE 1
CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features ■ High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.) True Dual-Ported memory cells which enable simultaneous access of the same memory location ■ 3.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Functional Description A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables enables easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Pin Configurations (continued NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC Figure 2.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Selection Guide CY7C09079V/89V/99V CY7C09179V/89V/99V-6[1] CY7C09079V/89V/99V CY7C09179V/89V/99V-7[1] CY7C09079V/89V/99V CY7C09179V/89V/99V -9 CY7C09079V/89V/99V CY7C09179V/89V/99V -12 fMAX2 (MHz) (Pipelined) 100 83 67 50 Max. Access Time (ns) (Clock to Data, Pipelined) 6.5 7.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Maximum Ratings Static Discharge Voltage............................................ >2001V Latch-Up Current ..................................................... >200 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[10] Operating Range Storage Temperature ................................. –65°C to +150°C Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 300 mV Industrial[11] –40°C to +85°C 3.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Figure 3. AC Test Loads 3.3V 3.3V R1 = 590Ω OUTPUT C = 30 pF OUTPUT R2 = 435Ω RTH = 250Ω R1 = 590Ω OUTPUT C = 30 pF C = 5 pF R2 = 435Ω VTH = 1.4V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) (b) Thévenin Equivalent (Load 1) Figure 4. AC Test Loads (Applicable to -6 and -7 only)[13] Z0 = 50Ω OUTPUT ALL INPUT PULSES R = 50Ω 3.0V C 10% GND 90% 10% 90% ≤ 3 ns ≤ 3 ns VTH = 1.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Characteristics Over the Operating Range CY7C09079V/89V/99V CY7C09179V/89V/99V Parameter Description -6[1] Min -7[1] Max Max Min -12 Max Unit fMAX1 fMax Flow-Through 53 45 40 33 MHz fMAX2 fMax Pipelined 100 83 67 50 MHz tCYC1 Clock Cycle Time - Flow-Through tCYC2 Clock Cycle Time - Pipelined tCH1 Clock HIGH Time - Flow-Through tCL1 Clock LOW Time - Flow-Through tCH2 Max Min 22 25 30 ns 10 12 15 20 ns 6.5 7.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 6. Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS An An+1 tCD1 DATAOUT An+2 tCKHZ tDC Qn tCKLZ An+3 Qn+1 Qn+2 tDC tOHZ tOLZ OE tOE Notes 16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 17. ADS = VIL, CNTEN and CNTRST = VIH. 18.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS An An+1 1 Latency DATAOUT An+2 An+3 tDC tCD2 Qn Qn+1 Qn+2 tOHZ tCKLZ tOLZ OE tOE Figure 8.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 9. Left Port Write to Flow-Through Right Port Read[22, 23, 24, 25] CLKL tSW tHW tSA tHA R/WL ADDRESSL NO MATCH MATCH tHD tSD DATAINL VALID tCCS CLKR R/WR tCD1 tSW tSA ADDRESSR tHW tHA NO MATCH MATCH tCWDD DATAOUTR tCD1 VALID tDC VALID tDC Notes 20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL)[19, 26, 27, 28] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS tSA An+1 An+2 tHA DATAIN tCD2 An+3 An+4 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Document #: 38-06043 Rev.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[19, 26, 27, 28] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 R/W ADDRESS tSW tHW tSW tHW An tSA An+1 An+2 tHA An+3 An+4 An+5 tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes 26. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 27.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 12. Flow-Through Read-to-Write-to-Read (OE = VIL)[17, 19, 26, 27, 28] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN An+2 An+2 tSD tHA An+3 tHD Dn+2 tCD1 tCD1 DATAOUT An+4 tCD1 Qn Qn+1 tDC tCKHZ READ tCD1 Qn+3 tCKLZ NO OPERATION WRITE tDC READ Figure 13.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 14. Pipelined Read with Address Counter Advance[29] tCH2 tCYC2 tCL2 CLK tSA tHA ADDRESS An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx READ EXTERNAL ADDRESS Qn tDC Qn+1 READ WITH COUNTER Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Figure 15.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 16. Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[30, 31] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 Dn+4 WRITE WITH COUNTER Notes 30. CE0 and R/W = VIL; CE1 and CNTRST = VIH. 31.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Figure 17. Counter Reset (Pipelined Outputs)[19, 26, 32, 33] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW tHW tSD tHD 1 An+1 An An+1 R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 Qn READ ADDRESS n Notes 32. CE0 = VIL; CE1 = VIH. 33. No dead cycle exists during counter reset.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Table 1. Read/Write and Enable Operation[34, 35, 36] Inputs OE CLK CE0 Outputs CE1 R/W I/O0–I/O9 Operation [37] X H X X High-Z Deselected X X L X High-Z Deselected[37] X L H L DIN Write L L H H DOUT Read[37] L H X High-Z Outputs Disabled H X Table 2.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Ordering Information 32K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5[1] CY7C09079V-6AC 7.
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CY7C09079V/89V/99V CY7C09179V/89V/99V 64K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1] 7.
PAGE 20
CY7C09079V/89V/99V CY7C09179V/89V/99V Package Diagram Figure 18. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 (51-85048) 51-85048-*B Document #: 38-06043 Rev.
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CY7C09079V/89V/99V CY7C09179V/89V/99V Document History Page Document Title: CY7C09079V/89V/99V, CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9Synchronous Dual Port Static RAM Document Number: 38-06043 Orig.