Static RAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1006D

1-Mbit (256K x 4) Static RAM

CY7C106D

CY7C1006D

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05459 Rev. *E Revised February 22, 2007

Features

• Pin- and function-compatible with CY7C106B/CY7C1006B

• High speed

—t

10 ns

• Low active power

—I

= 80 mA @ 10 ns

• Low CMOS standby power

—I

SB2

= 3.0 mA

• 2.0V Data Retention

• Automatic power-down when deselected

• CMOS for optimum speed/power

• TTL-compatible inputs and outputs

• CY7C106D available in Pb-free 28-pin 400-Mil wide Molded

SOJ package. CY7C1006D available in Pb-free 28-pin

300-Mil wide Molded SOJ package

Functional Description

[1]

The CY7C106D and CY7C1006D are high-performance

CMOS static RAMs organized as 262,144 words by 4 bits.

Easy memory expansion is provided by an active LOW Chip

Enable (CE

), an active LOW Output Enable (OE), and tri-state

drivers. These devices have an automatic power-down feature

that reduces power consumption by more than 65% when the

devices are deselected. The four input and output pins (IO

through IO

) are placed in a high-impedance state when:

• Deselected (CE

HIGH)

• Outputs are disabled (OE

HIGH)

• When the write operation is active (CE

and WE LOW)

Write to the device by taking Chip Enable (CE) and Write

Enable (WE

) inputs LOW. Data on the four IO pins (IO

through IO

) is then written into the location specified on the

address pins (A

through A

Read from the device by taking Chip Enable (CE) and Output

Enable (OE

) LOW while forcing Write Enable (WE) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins appears on the four IO pins.

Logic Block Diagram

SENSE AMPS

POWER

DOWN

ROW DECODER

256K x 4

ARRAY

INPUT BUFFER

COLUMN DECODER

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

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Summary of content (11 pages)

PAGE 1
CY7C106D CY7C1006D 1-Mbit (256K x 4) Static RAM Functional Description [1] Features • Pin- and function-compatible with CY7C106B/CY7C1006B • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10 ns • Low CMOS standby power — ISB2 = 3.0 mA The CY7C106D and CY7C1006D are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers.
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CY7C106D CY7C1006D Pin Configuration [2] SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC IO3 IO2 IO1 IO0 WE Selection Guide CY7C106D-10 CY7C1006D-10 Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum Standby Current 3 mA Note 2. NC pins are not connected on the die. Document #: 38-05459 Rev.
PAGE 3
CY7C106D CY7C1006D DC Input Voltage [3] ............................... –0.5V to VCC + 0.5V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current ....................
PAGE 4
CY7C106D CY7C1006D Capacitance [4] Parameter CIN: Addresses Description Test Conditions Input Capacitance Max Unit 7 pF TA = 25°C, f = 1 MHz, VCC = 5.0V CIN: Controls COUT Output Capacitance 10 pF 10 pF Thermal Resistance [4] Parameter Description Test Conditions ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 300-Mil Wide SOJ 400-Mil Wide SOJ Unit 59.16 58.76 °C/W 40.
PAGE 5
CY7C106D CY7C1006D Switching Characteristics (Over the Operating Range) [6] Parameter 7C106D-10 7C1006D-10 Description Min Unit Max Read Cycle tpower [7] VCC(typical) to the first access 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE tLZCE tHZCE tPU [10] tPD [10] Write Cycle 3 [8, 9] [9] 10 ns 5 ns CE HIGH to High Z CE LOW to Power-Up ns 5 3 [8,
PAGE 6
CY7C106D CY7C1006D Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [4] Chip Deselect to Data Retention Time tR [13, 14] Min Max 2.0 V VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Operation Recovery Time Unit 3 mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC 4.5V VDR > 2V tR tCDR CE Switching Waveforms Read Cycle No.
PAGE 7
CY7C106D CY7C1006D Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [18, 19] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [18, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD tHD DATA VALID DATA IO tHZOE Notes 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. Data IO is high impedance if OE = VIH. Document #: 38-05459 Rev.
PAGE 8
CY7C106D CY7C1006D Switching Waveforms (continued) Write Cycle No.
PAGE 9
CY7C106D CY7C1006D Package Diagrams Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031 NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE MIN. MAX. 3. DIMENSIONS IN INCHES DETAIL A EXTERNAL LEAD DESIGN PIN 1 ID 14 1 0.291 0.300 15 0.330 0.350 28 OPTION 1 0.697 0.713 A Document #: 38-05459 Rev. *E 0.014 0.020 OPTION 2 SEATING PLANE 0.120 0.140 0.050 TYP. 0.026 0.032 0.013 0.
PAGE 10
CY7C106D CY7C1006D Package Diagrams Figure 2. 28-pin (400-Mil) Molded SOJ, 51-85032 PIN 1 I.D 14 1 .395 .405 15 DIMENSIONS IN INCHES .435 .445 MIN. MAX. 28 .720 .730 SEATING PLANE .128 .148 .026 .032 .007 .013 0.004 .025 MIN. .360 .380 51-85032-*B .015 .020 All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05459 Rev. *E Page 10 of 11 © Cypress Semiconductor Corporation, 2006-2007.
PAGE 11
CY7C106D CY7C1006D Document History Page Document Title: CY7C106D/CY7C1006D, 1-Mbit (256K x 4) Static RAM Document Number: 38-05459 REV. ECN NO. Issue Date Orig.