18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1146V18

CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

18-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.0 Cycle Read Latency)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06621 Rev. *D Revised March 06, 2008

Features

■ 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz to 375 MHz clock for high bandwidth

■ 2-Word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 750 MHz) at 375 MHz

■ Read latency of 2.0 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Core V

= 1.8V ± 0.1V; IO V

DDQ

= 1.4V to V

[1]

■ HSTL inputs and Variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1-compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.0 cycles:

CY7C1146V18 – 2M x 8

CY7C1157V18 – 2M x 9

CY7C1148V18 – 1M x 18

CY7C1150V18 – 512K x 36

Functional Description

The CY7C1146V18, CY7C1157V18, CY7C1148V18, and

CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K

. Read data is driven on the rising edges

of K and K

. Each address location is associated with two 8-bit

words (CY7C1146V18) or 9-bit words (CY7C1157V18) or 18-bit

words (CY7C1148V18) or 36-bit words (CY7C1150V18) that

burst sequentially into or out of the device.

Asynchronous inputs include output impedance matching input

(ZQ). Synchronous data outputs (Q, sharing the same physical

pins as the data inputs D) are tightly matched to the two output

echo clocks CQ/CQ

, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the K or K

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 375 333 300 MHz

Maximum Operating Current 1020 920 850 mA

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

[+] Feedback [+] Feedback

Summary of content (27 pages)

PAGE 1
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description ■ 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz to 375 MHz clock for high bandwidth ■ 2-Word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces (data transferred at 750 MHz) at 375 MHz ■ Read latency of 2.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 K K DOFF CLK Gen. Write Reg Write Add. Decode LD Address Register Write Reg 1M x 8 Array 20 1M x 8 Array A(19:0) Read Add. Decode Logic Block Diagram (CY7C1146V18) 8 Output Logic Control R/W Read Data Reg. 16 VREF R/W CQ 8 Control Logic Reg. Reg. 8 CQ 8 8 NWS[1:0] DQ[7:0] 8 Reg. QVLD K K DOFF CLK Gen. Write Add. Decode LD Address Register Write Reg Write Reg 1M x 9 Array 20 1M x 9 Array A(19:0) Read Add.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 K K DOFF CLK Gen. Write Reg Write Add. Decode LD Address Register Write Reg 512K x 18 Array 19 512K x 18 Array A(18:0) Read Add. Decode Logic Block Diagram (CY7C1148V18) 18 Output Logic Control R/W Read Data Reg. 36 VREF R/W CQ 18 Control Logic Reg. 18 BWS[1:0] Reg. 18 18 Reg. CQ DQ[17:0] 18 QVLD K K DOFF CLK Gen. Write Add.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Pin Configurations 165-Ball FBGA (13 x 15 x 1.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Pin Configurations (continued) 165-Ball FBGA (13 x 15 x 1.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Pin Definitions Pin Name IO Pin Description DQ[x:0] Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks when write Synchronous operations are valid. These pins drive out the requested data when a read operation is active. Valid data is driven out on the rising edge of both the K and K clocks when read operations are active. When read access is deselected, Q[x:0] are automatically tri-stated.
PAGE 7
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Pin Definitions (continued) Pin Name DOFF IO Pin Description Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timings in the DLL turned off operation are different from those listed in this data sheet. For normal operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR-I mode when the DLL is turned off.
PAGE 8
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Functional Overview The CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 are synchronous pipelined Burst SRAMs equipped with a DDR interface. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input and output timings refer to the rising edge of the Input clocks (K/K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K/K).
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. DDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, “DLL Considerations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Write Cycle Descriptions The write cycle descriptions of CY7C1146V18 and CY7C1148V18 follows. [3, 9] BWS0/ BWS1/ K K L L–H – L L – L H L–H L H – H L L–H H L – H H L–H H H – NWS0 NWS1 L Comments When the Data portion of a write sequence is active: CY7C1146V18 − both nibbles (D[7:0]) are written into the device. CY7C1148V18 − both bytes (D[17:0]) are written into the device.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 The write cycle descriptions of CY7C1148V18 follows, [3, 9] BWS0 BWS1 BWS2 BWS3 K K L L L L L–H – L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – Document Number: 001-06621 Rev. *D Comments When the Data portion of a write sequence is active, all four bytes (D[35:0]) are written into the device.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard 1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
PAGE 13
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is supplied a test logic reset state.
PAGE 14
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 TAP Controller State Diagram Figure 2 shows the tap controller state diagram. [10] Figure 2. Tap Controller State Diagram 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note 10.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 TAP Controller Block Diagram Figure 3. Tap Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 1 0 1 0 Instruction Register 31 30 29 . . 2 Selection Circuitry TDO Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics The Tap Electrical Characteristics table over the operating range follows.
PAGE 16
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 TAP AC Switching Characteristics The Tap AC Switching Characteristics table over the operating range follows.
PAGE 17
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Identification Register Definitions Value Instruction Field CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 000 000 000 000 Cypress Device ID (28:12) 11010111100000101 11010111100001101 11010111100010101 Cypress JEDEC ID (11:1) 00000110100 00000110100 00000110100 00000110100 1 1 1 1 Revision Number (31:29) ID Register Presence (0) Description Version number. 11010111100100101 Defines the type of SRAM.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 1 6P 27 11H 54 7B 81 3G 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B
PAGE 19
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Power Up Sequence in DDR-II+ SRAM During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock. DDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
PAGE 20
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied –55°C to + 125°C Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Latch up Current.....................................................
PAGE 21
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max Unit 5 pF 6 pF 7 pF 165 FBGA Package Unit 17.2 °C/W 4.15 °C/W Thermal Resistance Tested initially and after any design or process change that may affect these parameters.
PAGE 22
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Switching Characteristics Over the operating range [21, 22] Cypress Consortium Parameter Parameter Description VDD(Typical) to the first Access[23] tPOWER 375 MHz 333 MHz 300 MHz Min Max Min Max Min Max 1 – tCYC tKHKH K Clock Cycle Time 2.66 8.40 Unit 1 – 1 – ms 3.0 8.40 3.3 8.40 ns tKH tKHKL Input Clock (K/K) HIGH 0.425 – 0.425 – 0.425 – tCYC tKL tKLKH Input Clock (K/K) LOW 0.425 – 0.425 – 0.
PAGE 23
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Switching Waveforms Read/Write/Deselect Sequence Figure 7. Waveform for 2.0 Cycle Read Latency[29, 30, 31] NOP 1 READ 2 NOP 4 READ 3 NOP 5 NOP 6 WRITE 7 WRITE 8 READ 9 NOP 10 NOP 11 12 K t KH tCYC t KL t KHKH K LD tSC tHC R/W A A0 t SA t HA A3 A2 A1 A4 t QVLD tQVLD t QVLD QVLD tHD t HD tSD Q00 DQ t Q01 Q10 tCO t CQOH CQ t CQOH D20 D21 D30 D31 Q40 Q41 t CHZ t DOH CLZ (Read Latency = 2.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Ordering Information Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 375 Ordering Code CY7C1146V18-375BZC Package Diagram Operating Range Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
PAGE 25
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 300 Ordering Code CY7C1146V18-300BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Package Diagram Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER Ø0.50 -0.06 (165X) +0.14 1 2 3 4 5 6 7 8 9 10 11 11 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D E F F G G H J 14.00 E 15.00±0.10 15.00±0.10 10 H J K L L 7.00 K M M N N P P R R A A 1.00 5.00 10.00 B B 13.00±0.10 13.00±0.10 1.40 MAX. 0.15 C 0.53±0.05 0.25 C 0.
PAGE 27
CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18 Document History Page Document Title: CY7C1146V18/CY7C1157V18/CY7C1148V18/CY7C1150V18, 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Document Number: 001-06621 REV. ECN No. Issue Date Orig.