18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Specification Sheet

CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Document Number: 001-06621 Rev. *D Page 21 of 27
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
DD
= 1.8V
V
DDQ
= 1.5V
5pF
C
CLK
Clock Input Capacitance 6 pF
C
O
Output Capacitance 7pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions
165 FBGA
Package
Unit
Θ
JA
Thermal Resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
17.2 °C/W
Θ
JC
Thermal Resistance
(junction to case)
4.15 °C/W
AC Test Loads and Waveforms
Figure 6. AC Test loads and Waveforms
1.25V
0.25V
R = 50Ω
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
DEVICE
R
L
= 50Ω
Z
0
= 50Ω
V
REF
= 0.75V
V
REF
= 0.75V
[21]
0.75V
UNDER
TEST
0.75V
DEVICE
UNDER
TEST
OUTPUT
0.75V
V
REF
V
REF
OUTPUT
ZQ
ZQ
(a)
SLEW RATE= 2 V/ns
RQ =
250
Ω
(b)
RQ =
250
Ω
Note
21. Unless otherwise noted, test conditions are based upon a signal transition time of 2V/ns, timing reference levels of 0.75V, V
REF
= 0.75V, RQ = 250Ω, V
DDQ
= 1.5V,
input pulse levels of 0.25V to 1.25V, and output loading of the specified I
OL
/I
OH
and load capacitance shown in (a) of AC Test Loads.
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