18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Specification Sheet

CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Document Number: 001-06621 Rev. *D Page 3 of 27
Logic Block Diagram (CY7C1148V18)
Logic Block Diagram (CY7C1150V18)
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS
[1:0]
V
REF
Write Add. Decode
18
18
LD
Control
19
512K x 18 Array
512K x 18 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
18
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS
[3:0]
V
REF
Write Add. Decode
36
36
LD
Control
18
256K x 36 Array
256K x 36 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
36
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