18-Mbit QDRTM-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1165V18

CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

18-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06582 Rev. *D Revised March 06, 2008

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 300 MHz to 400 MHz clock for high bandwidth

■ 4-word burst to reduce address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 800 MHz) at 400 MHz

■ Read latency of 2.5 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency providing most current data

■ Core V

= 1.8V ± 0.1V; IO V

DDQ

= 1.4V to V

[1]

■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With cycle read latency of 2.5 cycles:

CY7C1161V18 – 2M x 8

CY7C1176V18 – 2M x 9

CY7C1163V18 – 1M x 18

CY7C1165V18 – 512K x 36

Functional Description

The CY7C1161V18, CY7C1176V18, CY7C1163V18, and

CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs

equipped with QDR™-II+ architecture. QDR-II+ architecture

consists of two separate ports to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR-II+ architecture has separate data inputs and

data outputs to completely eliminate the need to turn around the

data bus that is required with common IO devices. Each port can

be accessed through a common address bus. Addresses for

read and write addresses are latched onto alternate rising edges

of the input (K) clock. Accesses to the QDR-II+ read and write

ports are completely independent of one another. In order to

maximize data throughput, both read and write ports are

equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with four 8-bit words

(CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words

(CY7C1163V18), or 36-bit words (CY7C1165V18) that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks K and K

, memory bandwidth is maximized while simpli-

fying system design by eliminating bus turnarounds.

Depth expansion is accomplished with port selects for each port.

Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the or K or K

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz

Maximum Operating Current 1080 1020 920 850 mA

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

[+] Feedback [+] Feedback

Summary of content (29 pages)

PAGE 1
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Functional Description ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth ■ 4-word burst to reduce address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz ■ Read latency of 2.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Logic Block Diagram (CY7C1161V18) DOFF Write Reg Address Register Read Add. Decode CLK Gen. Write Reg 512K x 8 Array K K Write Reg 512K x 8 Array 19 Write Reg 512K x 8 Array Address Register 512K x 8 Array A(18:0) 8 Write Add. Decode D[7:0] A(18:0) 19 RPS Control Logic Read Data Reg. 32 VREF WPS CQ 16 Reg. Control Logic NWS[1:0] CQ Reg. Q[7:0] 16 Reg.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Logic Block Diagram (CY7C1163V18) DOFF Write Reg Address Register Read Add. Decode CLK Gen. Write Reg 256K x 18 Array K K Write Reg 256K x 18 Array 18 Write Reg 256K x 18 Array Address Register 256K x 18 Array A(17:0) 18 Write Add. Decode D[17:0] 18 A(17:0) RPS Control Logic Read Data Reg. 72 VREF WPS CQ 36 Reg. Control Logic BWS[1:0] CQ 36 Reg. Q[17:0] Reg.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Pin Configurations 165-Ball FBGA (13 x 15 x 1.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Pin Configurations (continued) 165-Ball FBGA (13 x 15 x 1.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Pin Definitions Pin Name IO Pin Description D[x:0] InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. Synchronous CY7C1161V18−D[7:0] CY7C1176V18−D[8:0] CY7C1163V18−D[17:0] CY7C1165V18−D[35:0] WPS InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a write operation is initiated. Deasserting deselects the write port.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Pin Definitions (continued) Pin Name IO Pin Description CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics” on page 23. ZQ Input Output Impedance Matching Input. Used to tune the device outputs to the system data bus impedance. CQ, CQ and Q[x:0] output impedance are set to 0.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Functional Overview Write Operations The CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 are synchronous pipelined burst SRAMs equipped with both a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Depth Expansion Valid Data Indicator (QVLD) The CY7C1163V18 has a port select input for each port. This enables easy depth expansion. Both port selects are only sampled on the rising edge of the positive input clock (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Application Example Figure 1 shows four QDR-II+ used in an application. Figure 1. Application Example ZQ CQ/CQ SRAM #1 Q D A RPS WPS BWS K K Vt R RQ = 250ohms ZQ CQ/CQ SRAM #4 Q RPS WPS BWS K K D A DATA IN DATA OUT Address R R BUS MASTER RPS (CPU or ASIC) WPS RQ = 250ohms Vt Vt BWS CLKIN/CLKIN Source K Source K R = 50ohms, Vt = VDDQ /2 Truth Table The truth table for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Write Cycle Descriptions The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow.[3, 11] BWS0/ BWS1/ K K L L–H – L L – L H L–H L H – H L L–H H L – H H L–H H H – NWS0 NWS1 L Comments During the data portion of a write sequence: CY7C1161V18 − both nibbles (D[7:0]) are written into the device. CY7C1163V18 − both bytes (D[17:0]) are written into the device.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 The write cycle descriptions of CY7C1165V18 follows.[3, 11] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – Document Number: 001-06582 Rev.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard 1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 IDCODE The IDCODE instruction causes a vendor-specific 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 TAP Controller State Diagram Figure 2. Tap Controller State Diagram[12] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note 12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 TAP Controller Block Diagram Figure 3. Tap Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 1 0 1 0 Instruction Register 31 30 29 . . 2 Selection Circuitry TDO Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics The Tap Electrical Characteristics table over the operating range follows.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 TAP AC Switching Characteristics The Tap AC Switching Characteristics over the operating range follows.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Identification Register Definitions Instruction Field Value CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 000 000 000 000 Revision Number (31:29) Description Version number. Cypress Device ID 11010010001000101 11010010001001101 11010010001010101 11010010001100101 Defines the type of (28:12) SRAM.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 1 6P 27 11H 54 7B 81 3G 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Power Up Sequence in QDR-II+ SRA During power up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock. QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied. –55°C to + 125°C Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch up Current....................................................
PAGE 22
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max Unit 5 pF 6 pF 7 pF 165 FBGA Package Unit 17.2 °C/W 4.15 °C/W Thermal Resistance Tested initially and after any design or process change that may affect these parameters.
PAGE 23
CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Switching Characteristics Over the operating range[23, 24] Cypress Consortium Parameter Parameter Description VDD(Typical) to the First Access[25] tPOWER 400 MHz 375 MHz 333 MHz 300 MHz Min Max Min Max Min Max Min Max 1 – 1 – Unit 1 – 1 – ms tCYC tKHKH K Clock Cycle Time 2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40 ns tKH tKHKL Input Clock (K/K) HIGH 0.4 – 0.4 – 0.4 – 0.4 – tCYC tKL tKLKH Input Clock (K/K) LOW 0.4 – 0.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Switching Characteristics Over the operating range[23, 24] (continued) Cypress Consortium Parameter Parameter Description 400 MHz 375 MHz 333 MHz 300 MHz Min Max Min Max Min Max Min Max Unit DLL Timing tKC Var tKC Var Clock Phase Jitter tKC lock tKC lock DLL Lock Time (K) tKC Reset tKC Reset [30] K Static to DLL Reset – 0.20 – 0.20 – 0.20 – 0.20 ns 2048 – 2048 – 2048 – 2048 – Cycles 30 – 30 – 30 – 30 – ns Note 30.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Switching Waveforms Read/Write/Deselect Sequence Figure 6. Waveform for 2.5 Cycle Read Latency[31, 32, 33] NOP 1 WRITE 3 READ 2 READ 4 NOP 6 WRITE 5 7 8 K t KH t KL t CYC t KHKH K RPS t SC tHC t SC t HC WPS A A0 t SA A1 A3 A2 t HD t HA t SD D t HD t SD D10 D11 D12 D30 D13 D31 D32 tQVLD t QVLD QVLD D33 t CLZ tDOH t CO Q Q00 tCQDOH tCQD Q01 (Read Latency = 2.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Ordering Information Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 400 Ordering Code CY7C1161V18-400BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 333 Ordering Code CY7C1161V18-333BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Package Diagram Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER Ø0.50 -0.06 (165X) +0.14 1 2 3 4 5 6 7 8 9 10 11 11 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D E F F G G H J 14.00 E 15.00±0.10 15.00±0.10 10 H J K L L 7.00 K M M N N P P R R A A 1.00 5.00 10.00 B B 13.00±0.10 13.00±0.10 1.40 MAX. 0.15 C 0.53±0.05 0.25 C 0.
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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 Document History Page Document Title: CY7C1161V18/CY7C1176V18/CY7C1163V18/CY7C1165V18, 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Document Number: 001-06582 REV. ECN No. Issue Date Orig.