18-Mbit QDRTM-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Specification Sheet

CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Document Number: 001-06582 Rev. *D Page 15 of 29
TAP Controller State Diagram
Figure 2. Tap Controller State Diagram
[12]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
0
1
1
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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