18-Mbit Burst of 2 Pipelined SRAM with QDRTM Architecture Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1306BV25

18-Mbit Burst of 2 Pipelined SRAM with

DR™ Ar

tectu

CY7C1306BV25

CY7C1303BV25

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05627 Rev. *A Revised April 3, 2006

Features

• Separate independent Read and Write data ports

— Supports concurrent transactions

• 167-MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K

) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C

) to minimize

clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

• Variable Impedance HSTL

Configurations

CY7C1303BV25 – 1M x 18

CY7C1306BV25 – 512K x 36

Functional Description

The CY7C1303BV25 and CY7C1306BV25 are 2.5V

Synchronous Pipelined SRAMs equipped with QDR™ archi-

tecture. QDR architecture consists of two separate ports to

access the memory array. The Read port has dedicated Data

Outputs to support Read operations and the Write Port has

dedicated Data inputs to support Write operations. Access to

each port is accomplished through a common address bus.

The Read address is latched on the rising edge of the K clock

and the Write address is latched on the rising edge of K

clock.

QDR has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common I/O devices. Accesses to the CY7C1303BV25/

CY7C1306BV25 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock

(K). In order to maximize data throughput, both Read and

Write ports are equipped with Double Data Rate (DDR) inter-

faces. Therefore, data can be transferred into the device on

every rising edge of both input clocks (K and K

) and out of the

device on every rising edge of the output clock (C and C

, or K

and K

when in single clock mode) thereby maximizing perfor-

mance while simplifying system design. Each address location

is associated with two 18-bit words (CY7C1303BV25) or two

36-bit words (CY7C1306BV25) that burst sequentially into or

out of the device.

Depth expansion is accomplished with a Port Select input for

each port. Each Port Selects allow each port to operate

independently.

All synchronous inputs pass through input registers controlled

by the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

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Summary of content (19 pages)

PAGE 1
CY7C1303BV25 CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.
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CY7C1303BV25 CY7C1306BV25 Logic Block Diagram (CY7C1303BV25) D[17:0] 18 K CLK Gen. K 512Kx18 Memory Array Write Data Reg 512Kx18 Memory Array Read Add. Decode 19 Write Add. Decode Address Register A(18:0) Write Data Reg Address Register Control Logic Read Data Reg. 36 Vref WPS BWS0 18 Reg. Control Logic 18 A(18:0) 19 RPS C C Reg. 18 18 Reg. BWS1 Q[17:0] 18 Logic Block Diagram (CY7C1306BV25) D[35:0] 36 K CLK Gen.
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CY7C1303BV25 CY7C1306BV25 Pin Configuration 165-ball FBGA (13 x 15 x 1.
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CY7C1303BV25 CY7C1306BV25 Pin Definitions Name I/O Description D[x:0] InputData input signals, sampled on the rising edge of K and K clocks during valid write operaSynchronous tions. CY7C1303BV25 – D[17:0] CY7C1306BV25 – D[35:0] WPS InputWrite Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored.
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CY7C1303BV25 CY7C1306BV25 Pin Definitions (continued) Name I/O Description NC/36M N/A Address expansion for 36M. This pin is not connected to the die and so can be tied to any voltage level on CY7C1303BV25/CY7C1306BV25. GND/72M Input Address expansion for 72M. This pin has to be tied to GND on CY7C1303BV25. NC/72M N/A Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306BV25. GND/144M Input Address expansion for 144M.
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CY7C1303BV25 CY7C1306BV25 Depth Expansion operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-up.This function is a strap option and not alterable during device operation. The CY7C1303BV25 has a Port Select input for each port. This allows for easy depth expansion.
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CY7C1303BV25 CY7C1306BV25 Write Descriptions (CY7C1303BV25)[2, 8] BWS0 BWS1 K K Comments L L L-H - During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. L L - L-H During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. L H L-H - During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] remains unaltered.
PAGE 8
CY7C1303BV25 CY7C1306BV25 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
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CY7C1303BV25 CY7C1306BV25 is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
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CY7C1303BV25 CY7C1306BV25 TAP Controller State Diagram[9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 SHIFT-IR 0 SHIFT-DR 1 0 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-IR EXIT2-DR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05627 Rev.
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CY7C1303BV25 CY7C1306BV25 TAP Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 1 0 1 0 Instruction Register 31 30 29 . . 2 Selection Circuitry TDO Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range [10, 14, 17] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.7 V VOH2 Output HIGH Voltage IOH = −100 µA 2.
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CY7C1303BV25 CY7C1306BV25 TAP AC Switching Characteristics Over the Operating Range[11, 12] (continued) Parameter Description Min. Max. Unit Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 0 ns ns TAP Timing and Test Conditions[12] 1.25V 50Ω ALL INPUT PULSES TDO 2.5V Z0 = 50Ω (a) 1.
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CY7C1303BV25 CY7C1306BV25 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
PAGE 14
CY7C1303BV25 CY7C1306BV25 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D
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CY7C1303BV25 CY7C1306BV25 DC Input Voltage[17]............................... –0.5V to VDD + 0.5V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired.) Storage Temperature ................................ –65°C to + 150°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied............................................
PAGE 16
CY7C1303BV25 CY7C1306BV25 Capacitance[23] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance Test Conditions Max. TA = 25°C, f = 1 MHz, VDD = 2.5V. VDDQ = 1.5V Unit 5 pF 6 pF 7 pF AC Test Loads and Waveforms VREF = 0.75V 0.75V VREF VREF OUTPUT Z0 = 50Ω Device Under Test RL = 50Ω VREF = 0.75V ZQ 0.75V R = 50Ω ALL INPUT PULSES 1.25V 0.75V OUTPUT Device Under Test ZQ 5 pF [21] 0.
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CY7C1303BV25 CY7C1306BV25 Switching Waveforms[25, 26, 27] READ WRITE READ WRITE READ WRITE NOP WRITE NOP 1 2 3 4 5 6 7 8 9 10 K tKH tKL tCYC tKHKH K RPS tSC tHC WPS A A0 tSA D D10 A2 A1 tHA tSA D11 A3 A4 A5 D31 D50 D51 tHA D30 Q00 Q tKHCH tCO Q01 tDOH tCLZ D60 tSD tHD tSD tKHCH A6 Q20 tDOH D61 tHD Q21 Q40 Q41 tCHZ tCO C tKH tKL tKHKH tCYC C DON’T CARE UNDEFINED Notes: 24.
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CY7C1303BV25 CY7C1306BV25 Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed (MHz) 167 Package Diagram Ordering Code CY7C1303BV25-167BZC Operating Range Package Type 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1306BV25-167BZC CY7C1303BV25-167BZXC 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.
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CY7C1303BV25 CY7C1306BV25 Document History Page Document Title: CY7C1303BV25/CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture Document Number: 38-05627 Orig. of Change REV. ECN NO. Issue Date ** 253010 See ECN SYT New Data Sheet *A 436864 See ECN NXR Converted from Preliminary to Final. Removed 133 MHz & 100 MHz from product offering. Included the Industrial Operating Range. Changed C/C Description in the Features Section & Pin Description Table.