Static RAM Datasheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1318CV18-267BZXC

18-Mbit DDR II SRAM 2-Word

Burst Architecture

CY7C1318CV18

CY7C1320CV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-07160 Rev. *F Revised August 24, 2009

Features

■ 18-Mbit Density (1M x 18, 512K x 36)

■ 267 MHz Clock for high Bandwidth

■ 2-word Burst for reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces

(data transferred at 534 MHz) at 267 MHz

■ Two Input Clocks (K and K) for precise DDR Timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Synchronous internally Self-timed Writes

■ DDR II operates with 1.5 Cycle Read Latency when the DLL is

enabled

■ Operates similar to a DDR I Device with one Cycle Read

Latency in DLL Off Mode

■ 1.8V Core Power Supply with HSTL Inputs and Outputs

■ Variable drive HSTL Output Buffers

■ Expanded HSTL Output Voltage (1.4V–V

)

■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ JTAG 1149.1 compatible Test Access Port

■ Delay Lock Loop (DLL) for accurate Data Placement

Configurations

CY7C1318CV18 – 1M x 18

CY7C1320CV18 – 512K x 36

Functional Description

The CY7C1318CV18, and CY7C1320CV18 are 1.8V

Synchronous Pipelined SRAMs equipped with DDR II archi-

tecture. The DDR II consists of an SRAM core with advanced

synchronous peripheral circuitry and a one-bit burst counter.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K

. Read data is driven on the rising edges

of C and C

if provided, or on the rising edge of K and K if C/C are

not provided. For CY7C1318CV18 and CY7C1320CV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words (in the case of

CY7C1318CV18) of two 36-bit words (in the case of

CY7C1320CV18) sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C

) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 267 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 267 250 200 167 MHz

Maximum Operating Current x18 805 730 600 510 mA

x36 855 775 635 540

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Summary of content (26 pages)

PAGE 1
CY7C1318CV18 CY7C1320CV18 18-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description ■ 18-Mbit Density (1M x 18, 512K x 36) ■ 267 MHz Clock for high Bandwidth ■ 2-word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces (data transferred at 534 MHz) at 267 MHz ■ Two Input Clocks (K and K) for precise DDR Timing ❐ SRAM uses rising edges only ■ Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches ■ Echo Clocks
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CY7C1318CV18 CY7C1320CV18 Logic Block Diagram (CY7C1318CV18) A(19:1) LD K Address Register CLK Gen. K Write Add. Decode 19 DOFF Write Reg Write Reg 512K x 18 Array 20 512K x 18 Array A(19:0) Read Add. Decode Burst Logic A0 18 Output Logic Control R/W C Read Data Reg. 36 VREF Control Logic R/W BWS[1:0] C 18 18 Reg. Reg. 18 Reg. 18 CQ CQ 18 DQ[17:0] Logic Block Diagram (CY7C1320CV18) A(18:1) LD K K Address Register CLK Gen. DOFF VREF R/W BWS[3:0] Write Add.
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CY7C1318CV18 CY7C1320CV18 Pin Configuration The pin configuration for CY7C1318CV18 and CY7C1320CV18 follow.[1] 165-Ball FBGA (13 x 15 x 1.
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CY7C1318CV18 CY7C1320CV18 Pin Definitions Pin Name I/O Pin Description DQ[x:0] Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write Synchronous operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode. When read access is deselected, Q[x:0] are automatically tristated.
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CY7C1318CV18 CY7C1320CV18 Pin Definitions Pin Name DOFF (continued) I/O Pin Description Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR I mode when the DLL is turned off.
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CY7C1318CV18 CY7C1320CV18 Functional Overview The CY7C1318CV18, and CY7C1320CV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS the device behaves in DDR I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K).
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CY7C1318CV18 CY7C1320CV18 Programmable Impedance DLL An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V.
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CY7C1318CV18 CY7C1320CV18 Truth Table The truth table for the CY7C1318CV18, and CY7C1320CV18 follows.[2, 3, 4, 5, 6, 7] K LD R/W Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Operation L-H L L D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑ Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges.
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CY7C1318CV18 CY7C1320CV18 Write Cycle Descriptions The write cycle description table for CY7C1320CV18 follows.[2, 8] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – Document Number: 001-07160 Rev.
PAGE 10
CY7C1318CV18 CY7C1320CV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
PAGE 11
CY7C1318CV18 CY7C1320CV18 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state.
PAGE 12
CY7C1318CV18 CY7C1320CV18 TAP Controller State Diagram The state diagram for the TAP controller follows.[9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 PAUSE-DR 0 0 0 1 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
PAGE 13
CY7C1318CV18 CY7C1320CV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 106 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[10, 11, 12] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V VOH2 Output HIGH Voltage IOH = −100 μA 1.
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CY7C1318CV18 CY7C1320CV18 TAP AC Switching Characteristics Over the Operating Range[13, 14] Parameter Description Min Max Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns 50 n
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CY7C1318CV18 CY7C1320CV18 Identification Register Definitions Value Instruction Field Description CY7C1318CV18 CY7C1320CV18 000 000 Cypress Device ID (28:12) 11010100010010101 11010100010100101 Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicates the presence of an ID register. Revision Number (31:29) Version number. Defines the type of SRAM.
PAGE 16
CY7C1318CV18 CY7C1320CV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P 29 9G 57 5B 85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N 32 9F 60 5C 88 1K 5 7R 33 10F 61 4B 89 2L 6 8R 34 11E 62 3A 90 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C
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CY7C1318CV18 CY7C1320CV18 Power Up Sequence in DDR II SRAM DLL Constraints DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior.
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CY7C1318CV18 CY7C1320CV18 Maximum Ratings Neutron Soft Error Immunity Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Parameter Storage Temperature ................................. –65°C to +150°C LSBU Logical Single-Bit Upsets 25°C LMBU Logical Multi-Bit Upsets Single Event Latch up Ambient Temperature with Power Applied.. –55°C to +125°C Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V Supply Voltage on VDDQ Relative to GND..
PAGE 19
CY7C1318CV18 CY7C1320CV18 Electrical Characteristics (continued) DC Electrical Characteristics Over the Operating Range[12] Parameter Description ISB1 Automatic Power Down Current Test Conditions Max VDD, 267 MHz Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL 250 MHz f = fMAX = 1/tCYC, Inputs Static 200 MHz 167 MHz Min Typ Max 315 330 300 320 290 300 285 295 Unit mA Min VREF + 0.2 – Typ – – Max – VREF – 0.
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CY7C1318CV18 CY7C1320CV18 Switching Characteristics Over the Operating Range[20, 21] Cypress Consortium Parameter Parameter Description VDD(Typical) to the First Access [22] tPOWER 267 MHz 250 MHz 200 MHz 167 MHz Min Max Min Max Min Max Min Max Unit 1 – 1 – 1 – 1 – ms tCYC tKHKH K Clock and C Clock Cycle Time 3.75 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns tKH tKHKL Input Clock (K/K and C/C) HIGH 1.5 – 1.6 – 2.0 – 2.4 – ns tKL tKLKH Input Clock (K/K and C/C) LOW 1.5 – 1.
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CY7C1318CV18 CY7C1320CV18 Switching Characteristics (continued) Over the Operating Range[20, 21] Cypress Consortium Parameter Parameter Description 267 MHz 250 MHz 200 MHz 167 MHz Min Max Min Max Min Max Min Max Unit Output Times tCO tCHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid – 0.45 – 0.45 – 0.45 – 0.50 ns tDOH tCHQX Data Output Hold after Output C/C Clock Rise (Active to Active) –0.45 – –0.45 – –0.45 – –0.
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CY7C1318CV18 CY7C1320CV18 Switching Waveforms Figure 5. Read/Write/Deselect Sequence[26, 27, 28] READ 2 NOP 1 READ 3 NOP 4 NOP 5 WRITE 6 WRITE 7 READ 8 A3 A4 9 10 K tKH tKL tKHKH tCYC K LD tSC tHC R/W A A0 tSA A2 A1 tHD tHA tHD tSD DQ Q00 t KHCH t CLZ Q01 Q10 Q11 tSD D20 D21 D30 D31 Q40 Q41 t CQDOH t CHZ tDOH tCO t CQD C t KHCH tKH tKL tCYC tKHKH C# tCQOH tCCQO CQ tCQOH tCCQO tCQH tCQHCQH CQ# DON’T CARE UNDEFINED Notes 26.
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CY7C1318CV18 CY7C1320CV18 Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors.
PAGE 24
CY7C1318CV18 CY7C1320CV18 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 TOP VIEW BOTTOM VIEW PIN 1 CORNER PIN 1 CORNER Ø0.08 M C 1 2 3 4 5 6 7 8 9 10 11 Ø0.25 M C A B A Ø0.50 -0.06 (165X) +0.14 B 11 10 9 8 7 6 5 4 3 2 1 C A D B E C 1.00 F D G 15.00±0.10 E H F J L M 14.00 15.00±0.10 G K H J K N L 7.00 P M R N P A R A 1.00 5.00 B 13.00±0.10 1.40 MAX. C 0.35±0.06 0.36 SEATING PLANE 0.15 C 0.53±0.05 0.25 C 10.00 B 13.00±0.10 0.
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CY7C1318CV18 CY7C1320CV18 Document History Page Document Title: CY7C1318CV18/CY7C1320CV18, 18-Mbit DDR II SRAM 2-Word Burst Architecture Document Number: 001-07160 Rev. ECN No. Submission Date Orig.
PAGE 26
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