Static RAM Datasheet

CY7C1318CV18
CY7C1320CV18
Document Number: 001-07160 Rev. *F Page 22 of 26
Switching Waveforms
Figure 5. Read/Write/Deselect Sequence
[26, 27, 28]
READ READREAD NOP NOP WRITEWRITE
NOP
1
2345678910
Q40
t
KHCH
t
CO
t
t
HC
t
t
HA
t
SD
t
HD
t
KHCH
t
SD
t
HD
DON’T CARE
UNDEFINED
t
CLZ
t
DOH
t
CHZ
SC
t
KH
t
KHKH
t
KL
t
CYC
A0
D20
D21 D30
D31
Q00 Q11Q01 Q10
A1
A2
A3
A4
Q41
t
CCQO
t
CQOH
t
CCQO
t
CQOH
t
KL
t
CYC
K
K
LD
R/W
A
DQ
C
C#
CQ
CQ#
SA
t
KH
t
KHKH
t
CQD
t
CQDOH
t
CQH
t
CQHCQH
Notes
26. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
27. Outputs are disabled (High-Z) one clock cycle after a NOP.
28. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
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