4-Mbit (128K x 36) Pipelined SRAM with NoBLTM Architecture Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1350G

4-Mbit (128K x 36) Pipelined SRAM

with NoBL™ Architecture

CY7C1350G

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05524 Rev. *F Revised July 5, 2006

Features

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Byte Write capability

• 128K x 36 common I/O architecture

• 3.3V power supply (V

)

• 2.5V/3.3V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable (OE

)

• Available in lead-free 100-Pin TQFP package, lead-free

and non-lead-free 119-Ball BGA package

• Burst Capability—linear or interleaved burst order

• “ZZ” Sleep mode option

Functional Description

[1]

The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1350G is equipped with the advanced

No Bus Latency™ (NoBL™) logic required to enable consec-

utive Read/Write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of the SRAM, especially in systems that require

frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN

) signal,

which, when deasserted, suspends operation and extends the

previous clock cycle. Maximum access delay from the clock

rise is 2.6 ns (250-MHz device)

Write operations are controlled by the four Byte Write Select

(BW

[A:D]

) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

INPUT

CLK

WRITE

DRIVERS

SLEEP

CONTROL

agram

[+] Feedback

Summary of content (15 pages)

PAGE 1
CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 128K x 36 common I/O architecture • 3.3V power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) The CY7C1350G is a 3.
PAGE 2
CY7C1350G Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit Maximum Access Time 2.6 2.8 3.5 4.0 4.
PAGE 3
CY7C1350G Pin Configurations (continued) 119-Ball BGA Pinout A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ A A NC/18M A A VDDQ NC/576M CE2 A A A DQPC A VSS A VSS CE3 A DQPB NC NC/1G DQC ADV/LD VDD NC NC DQB DQC DQC VSS CE1 VSS DQB DQB VDDQ DQC VSS OE VSS DQB VDDQ DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS VSS VSS NC/9M BWB VSS VSS VSS DQB DQB VDD DQA DQB DQB VDDQ DQA DQD VDDQ DQD DQD BWD VSS BWA VSS DQA DQA DQA VDDQ DQD DQD VSS CEN A1 VSS DQA
PAGE 4
CY7C1350G Pin Definitions (continued) Name I/O Description ZZ InputAsynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ pin has an internal pull-down. DQs I/OSynchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK.
PAGE 5
CY7C1350G On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQP[A:D]. In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).
PAGE 6
CY7C1350G Truth Table[2, 3, 4, 5, 6, 7, 8] (continued) CE ZZ ADV/LD CLK DQ NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H — SNOOZE MODE None X H X X X X X X Tri-State Operation Address Used WE BWx OE CEN Partial Truth Table for Read/Write[2, 3, 9] Function WE BWD BWC BWB BWA Read H X X X X Write − No bytes written L
PAGE 7
CY7C1350G DC Input Voltage ....................................... −0.5V to VDD + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied.................................................. −55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage...........................................
PAGE 8
CY7C1350G Electrical Characteristics Over the Operating Range[10, 11] (continued) Parameter ISB3 Description Test Conditions Automatic CE Power-Down Current—CMOS Inputs ISB4 VDD = Max, Device Deselected, or VIN ≤ 0.3V or VIN > VDDQ – 0.3V f = fMAX = 1/tCYC Automatic CE Power-Down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 Max. Unit 4-ns cycle, 250 MHz Min. 105 mA 5-ns cycle, 200 MHz 95 mA 6-ns cycle, 166 MHz 85 mA 7.
PAGE 9
CY7C1350G Switching Characteristics Over the Operating Range[17, 18] –250 Parameter tPOWER Description [13] VDD (typical) to the first Access –200 –166 Max. –133 –100 Min. Max. Min. Max. Min. Min. Max. Min. Max. Unit 1 1 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5.0 6.0 7.5 10 ns tCH Clock HIGH 1.7 2.0 2.5 3.0 3.5 ns tCL Clock LOW 1.7 2.0 2.5 3.0 3.5 ns Output Times tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise [14, 15, 16] 2.6 1.0 2.
PAGE 10
CY7C1350G Switching Waveforms Read/Write Timing[19, 20, 21] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BW[A:D] A1 ADDRESS A2 tCO tAS tDS tAH Data tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) In-Out (DQ) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINED No
PAGE 11
CY7C1350G Switching Waveforms (continued) NOP, STALL, and DESELECT Cycles[19, 20, 22] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW[A:D] ADDRESS A5 tCHZ D(A1) Data In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) DON’T CARE Q(A2) D(A4) Q(A3) WRITE D(A4) STALL NOP READ Q(A5) Q(A5) DESELECT CONTINUE DESELECT UNDEFINED ZZ Mode Timing[23, 24] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z
PAGE 12
CY7C1350G Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 100 Ordering Code 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-100BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1350G-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 13
CY7C1350G Package Diagrams 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 81 100 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0.10 1.60 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
PAGE 14
CY7C1350G Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 1 2 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C D 1.27 C D E E F F H 19.50 J K L 20.32 G H 22.00±0.20 G J K L M 10.16 M N P N P R R T T U U 1.27 0.70 REF. A 3.81 7.62 30° TYP. 14.00±0.20 0.15(4X) 0.15 C 2.40 MAX. B 0.90±0.05 0.25 C 12.00 51-85115-*B C 60±0.10 0.
PAGE 15
CY7C1350G Document History Page Document Title: CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05524 REV. Issue ECN NO. Date Orig.