Pipelined SRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1356CV25

9-Mbit (256K x 36/512K x 18)

elined SRAM with NoBL™ Architecture

CY7C1354CV25

CY7C1356CV25

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05537 Rev. *H Revised September 14, 2006

Features

• Pin-compatible with and functionally equivalent to

ZBT™

• Supports 250-MHz bus operations with zero wait states

• Available speed grades are 250, 200, and 166 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 2.5V power supply (V

)

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability–linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

[1]

The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x

36 and 512K x 18 Synchronous pipelined burst SRAMs with

No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations with no wait states. The CY7C1354CV25 and

CY7C1356CV25 are equipped with the advanced (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data in systems that

require frequent Write/Read transitions. The CY7C1354CV25

and CY7C1356CV25 are pin-compatible with and functionally

equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN

) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW

–BW

for CY7C1354CV25 and BW

–BW

for

CY7C1356CV25) and a Write Enable (WE

) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

INPUT

CLK

WRITE

DRIVERS

SLEEP

CONTROL

Logic Block Diagram–CY7C1354CV25 (256K x 36)

[+] Feedback

Summary of content (28 pages)

PAGE 1
CY7C1354CV25 CY7C1356CV25 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture Functional Description[1] Features • Pin-compatible with and functionally equivalent to ZBT™ The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states.
PAGE 2
CY7C1354CV25 CY7C1356CV25 Logic Block Diagram–CY7C1356CV25 (512K x 18) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD BWa WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY BWb S E N S E A M P S WE O U T P U T R E G I S T E R S D A T A S T E E R I N G E INPUT REGISTER 1 E OE CE1 CE2 CE3 ZZ O U T P U T B U F F E R S DQs DQPa DQPb E INPUT REGISTER 0 E READ LOGIC
PAGE 3
CY7C1354CV25 CY7C1356CV25 Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1356CV25 (512K × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A A A A A A A NC(72M) NC(36M) VSS VDD NC(288M) NC(144M) A A A A A A A NC(72M) 31 32 3
PAGE 4
CY7C1354CV25 CY7C1356CV25 Pin Configurations (continued) 119-Ball BGA Pinout CY7C1354CV25 (256K × 36) 1 2 3 4 5 6 7 A VDDQ A A NC/18M A A VDDQ B C D E F G H J K L M N P NC/576M NC/1G DQc CE2 A DQPc A A VSS ADV/LD VDD NC A A VSS CE3 A DQPb NC NC DQb CE1 VSS DQb DQb OE A VSS DQb VDDQ BWb DQb DQb WE VDD VSS NC DQb VDD DQb VDDQ CLK NC VSS BWa DQa DQa DQa DQa R T U DQc DQc VSS VDDQ DQc VSS DQc DQc DQc VDDQ DQc VDD BWc VSS NC DQd DQd DQd DQd BWd VDDQ DQd
PAGE 5
CY7C1354CV25 CY7C1356CV25 Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1354CV25 (256K × 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/576M A CE1 BWc BWb CE3 ADV/LD A A NC CLK CEN WE OE NC/18M VSS VSS VSS VDD VDDQ VDDQ A NC DQb DQPb DQb VDDQ DQb DQb R MODE NC/1G A CE2 DQPc DQc NC DQc VDDQ VDDQ BWd VSS VDD BWa VSS VSS VSS VSS DQc DQc VDDQ VDD VSS VSS VSS VDD NC DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc NC DQd DQ
PAGE 6
CY7C1354CV25 CY7C1356CV25 Pin Definitions Pin Name I/O Type Pin Description A0 A1 A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. BWa,BWb, BWc,BWd, InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.
PAGE 7
CY7C1354CV25 CY7C1356CV25 Pin Definitions (continued) Pin Name I/O Type Pin Description NC – No connects. This pin is not connected to the die. NC (18, 36, 72, 144, 288, 576, 1G – These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M 288M, 576M, and 1G densities. InputAsynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved.
PAGE 8
CY7C1354CV25 CY7C1356CV25 order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1354CV25 and CY7C1356CV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b for CY7C1356CV25) inputs. Doing so will tri-state the output drivers.
PAGE 9
CY7C1354CV25 CY7C1356CV25 Truth Table[2, 3, 4, 5, 6, 7, 8] Operation NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SLEEP MODE Address Used None Next Current None CE ZZ L L X L X L X H ADV/LD L H X X WE L X X X BWx H H X X OE X X X X CEN L L H X CLK L-H L-H L-H X DQ Tri-State Tri-State – Tri-State Partial Write Cycle Description[2, 3, 4, 9] Function (CY7C1354CV25) Read WE H BWd BWc BWb BWa X X X X Write –No bytes written L H H H H Write Byte a–
PAGE 10
CY7C1354CV25 CY7C1356CV25 IEEE 1149.1 Serial Boundary Scan (JTAG) The ball is pulled up internally, resulting in a logic HIGH level. The CY7C1354CV25/CY7C1356CV25 incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance.
PAGE 11
CY7C1354CV25 CY7C1356CV25 It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.
PAGE 12
CY7C1354CV25 CY7C1356CV25 TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[11, 12] Parameter Description Min. Max.
PAGE 13
CY7C1354CV25 CY7C1356CV25 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent 1.25V Input pulse levels ............................................... VSS to 2.5V Input rise and fall time .................................................... 1 ns 50Ω Input timing reference levels ........................................1.25V Output reference levels ................................................1.25V TDO Test load termination supply voltage.............................1.
PAGE 14
CY7C1354CV25 CY7C1356CV25 Boundary Scan Exit Order (256K × 36) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 119-ball ID K4 H4 M4 F4 B4 G4 C3 B3 D6 H7 G6 E6 D7 E7 F6 G7 H6 T7 K7 L6 N6 P7 N7 M6 L7 K6 P6 T4 A3 C5 B5 A5 C6 A6 P4 N4 R6 T5 T3 R2 R3 P2 P1 L2 K1 N2 N1 Document #: 38-05537 Rev.
PAGE 15
CY7C1354CV25 CY7C1356CV25 Boundary Scan Exit Order (512K × 18) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 119-ball ID K4 H4 M4 F4 B4 G4 C3 B3 T2 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) D6 E7 F6 G7 H6 T7 K7 L6 N6 P7 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) T6 A3 C5 B5 A5 C6 A6 P4 N4 R6 T5 T3 R2 R3 Document #: 38-0
PAGE 16
CY7C1354CV25 CY7C1356CV25 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V DC Input Voltage...............
PAGE 17
CY7C1354CV25 CY7C1356CV25 Capacitance[16] Parameter Test Conditions 100 TQFP Max. TA = 25°C, f = 1 MHz, VDD = 2.5V, VDDQ = 2.5V 5 5 5 pF 5 5 5 pF 5 7 7 pF Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance 119 BGA Max. 165 FBGA Max.
PAGE 18
CY7C1354CV25 CY7C1356CV25 Switching Characteristics Over the Operating Range [18, 19] –250 –200 Parameter Description Min. [17] VCC (typical) to the First Access Read or Write 1 1 1 ms 4.0 5 6 ns tPower Max. Min. –166 Max. Min. Max. Unit Clock tCYC Clock Cycle Time FMAX Maximum Operating Frequency tCH Clock HIGH 1.8 2.0 2.4 ns tCL Clock LOW 1.8 2.0 2.4 ns 250 200 166 MHz Output Times tCO Data Output Valid after CLK Rise 2.8 3.2 3.
PAGE 19
CY7C1354CV25 CY7C1356CV25 Switching Waveforms Read/Write Timing[23, 24, 25] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWX A1 ADDRESS A2 tCO tAS tDS tAH Data tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) n-Out (DQ) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UN
PAGE 20
CY7C1354CV25 CY7C1356CV25 Switching Waveforms (continued) NOP, STALL and DESELECT CYCLES[23, 24, 26] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BWX ADDRESS A5 tCHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL DON’T CARE NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Note: 26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause.
PAGE 21
CY7C1354CV25 CY7C1356CV25 Switching Waveforms (continued) ZZ Mode Timing[27, 28] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I t RZZI DDZZ ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05537 Rev.
PAGE 22
CY7C1354CV25 CY7C1356CV25 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 166 Ordering Code CY7C1354CV25-166AXC Package Diagram Operating Range Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356CV25-166AXC CY7C1354CV25-166BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 23
CY7C1354CV25 CY7C1356CV25 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. 200 CY7C1354CV25-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356CV25-200AXC CY7C1354CV25-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 24
CY7C1354CV25 CY7C1356CV25 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. 250 CY7C1354CV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356CV25-250AXC CY7C1354CV25-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 25
CY7C1354CV25 CY7C1356CV25 Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2.
PAGE 26
CY7C1354CV25 CY7C1356CV25 Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 1 2 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C D 1.27 C D E E F F H 19.50 J K L 20.32 G H 22.00±0.20 G J K L M 10.16 M N P N P R R T T U U 1.27 0.70 REF. A 3.81 7.62 30° TYP. 14.00±0.20 0.15(4X) 0.15 C 2.40 MAX. B 0.90±0.05 0.25 C 12.00 51-85115-*B C Document #: 38-05537 Rev. *H 0.60±0.10 0.
PAGE 27
CY7C1354CV25 CY7C1356CV25 Package Diagrams (continued) 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER Ø0.50 -0.06 (165X) +0.14 1 2 3 4 5 6 7 8 9 10 11 11 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D E F F G G H J 14.00 E 15.00±0.10 15.00±0.10 10 H J K L L 7.00 K M M N N P P R R A A 1.00 5.00 10.00 B B 13.00±0.10 13.00±0.10 1.40 MAX. 0.15 C 0.53±0.05 0.25 C 0.
PAGE 28
CY7C1354CV25 CY7C1356CV25 Document History Page Document Title: CY7C1354CV25/CY7C1356CV25 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05537 REV. ECN No. Issue Date Orig.