Pipelined SRAM Specification Sheet

CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *H Page 7 of 28
Functional Overview
The CY7C1354CV25 and CY7C1356CV25 are
synchronous-pipelined Burst NoBL SRAMs designed specifi-
cally to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN
). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
CO
) is 2.8 ns (250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN
) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
). BW
[d:a]
can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
). All
Writes are simplified with on-chip synchronous self-timed
Write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE
) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE
is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.8 ns
(250-MHz device) provided OE
is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1354CV25 and CY7C1356CV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi-
ciently. A HIGH input on ADV/LD
will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to A
0
∠A
16
is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
input signal. This
allows the external logic to present the data on DQ
and DQP
(DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1354CV25 and DQ
a,b
/DQP
a,b
for CY7C1356CV25). In addition, the address for the subse-
quent access (Read/Write/Deselect) is latched into the
address register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
and DQP
(DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1354CV25 and DQ
a,b
/DQP
a,b
for CY7C1356CV25) (or a subset for byte write operations,
see Write Cycle Description table for details) inputs is latched
into the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BW
a,b,c,d
for CY7C1354CV25 and BW
a,b
for
CY7C1356CV25) signals. The CY7C1354CV25/56CV25
provides Byte Write capability that is described in the Write
Cycle Description table. Asserting the Write Enable input (WE
)
with the selected Byte Write Select (BW
) input will selectively
write to only the desired bytes. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
Write operations. Byte Write capability has been included in
NC – No connects. This pin is not connected to the die.
NC (18,
36, 72,
144, 288,
576, 1G
– These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
288M, 576M, and 1G densities.
ZZ Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
Pin Definitions (continued)
Pin Name I/O Type Pin Description
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