Pipelined DCD Sync SRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1386D

18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-05545 Rev. *E Revised Feburary 09, 2007

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (double-cycle deselect)

• Depth expansion without wait state

• 3.3V core power supply (V

)

• 2.5V or 3.3V IO power supply (V

DDQ)

• Fast clock-to-output times

— 2.6 ns (for 250 MHz device)

• Provides high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self timed writes

• Asynchronous output enable

• CY7C1386D/CY7C1387D available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball

FBGA package. CY7C1386F/CY7C1387F available in

Pb-free and non Pb-free 119-ball BGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

Functional Description

[1]

The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

SRAM integrates 512K x 36/1M x 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive edge triggered clock

input (CLK). The synchronous inputs include all addresses, all

data inputs, address-pipelining chip enable (CE

), depth

expansion chip enables (CE

and

[2]

), burst control inputs

(ADSC

, ADSP,

and

ADV), write enables (

, and BWE), and

global write (GW

). Asynchronous inputs include the output

enable (OE

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP

) or

address strobe controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the advance pin (ADV

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see Pin Configurations on page 3 and Truth Table

[4, 5, 6, 7, 8]

on page 9 for further details). Write cycles can be

one to four bytes wide as controlled by the byte write control

inputs. GW

active LOW causes all bytes to be written. This

device incorporates an additional pipelined enable register

which delays turning off the output buffers an additional cycle

when a deselect is executed.This feature allows depth

expansion without penalizing system performance.

The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

operates from a +3.3V core power supply while all outputs

operate with a +3.3V or +2.5V supply. All inputs and outputs

are JEDEC-standard and JESD8-5-compatible.

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.0 3.4 ns

Maximum Operating Current 350 300 275 mA

Maximum CMOS Standby Current 70 70 70 mA

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE

and CE

are for TQFP and 165 FBGA packages only. 119 BGA is offered only in Single Chip Enable.

[+] Feedback

Summary of content (30 pages)

PAGE 1
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F SRAM integrates 512K x 36/1M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).
PAGE 2
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Logic Block Diagram – CY7C1386D/CY7C1386F [3] (512K x 36) ADDRESS REGISTER A0,A1,A 2 A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP BW D DQ D, DQP D BYTE WRITE REGISTER DQ D, DQP D BYTE WRITE DRIVER BW C DQ c ,DQP C BYTE WRITE REGISTER DQ c ,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE DRIVER BW B GW CE 1 CE 2 CE 3 OE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQP A DQP B DQP C DQP D E
PAGE 3
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Configurations NC NC NC CY7C1387D (1M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document Number: 38-05545 Rev.
PAGE 4
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Configurations (continued) 119-Ball BGA Pinout (1 Chip Enable) CY7C1386F (512K x 36) 1 A VDDQ 2 A 3 A A 4 ADSP 5 A 6 A VDDQ B C NC/288M NC/144M A A A ADSC VDD A A A A NC/576M NC/1G D E DQC DQC DQPC DQC VSS VSS NC CE1 VSS VSS DQPB DQB DQB DQB F VDDQ DQC VSS OE VSS DQB VDDQ G H J K DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS NC VSS ADV BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA BWA VSS DQA DQA DQA VDDQ GW VDD CLK NC
PAGE 5
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1386D (512K x 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288M A CE1 BWC BWB CE3 BWE ADSC ADV A NC NC/144M A CE2 BWD BWA CLK OE NC/512M NC DQC VDDQ VSS VDDQ VSS VDD VSS VSS VSS ADSP VDDQ A DQPC DQC GW VSS VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS DQC DQC VDDQ VDD VSS DQC NC DQD DQC NC DQD VDDQ NC VDDQ VDD VDD VDD DQD
PAGE 6
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Definitions Name IO Description A0, A1, A InputSynchronous Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2] are sampled active. A1: A0 are fed to the two-bit counter. BWA, BWB BWC, BWD InputSynchronous Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK.
PAGE 7
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Definitions (continued) Name IO VSS Ground Description Ground for the core of the device. VSSQ IO Ground VDDQ IO Power Supply Ground for the IO circuitry. MODE InputStatic Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up.
PAGE 8
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BWX signals.
PAGE 9
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Truth Table [4, 5, 6, 7, 8] Add.
PAGE 10
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Truth Table for Read/Write [6, 9] Function (CY7C1386D/CY7C1386F) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A – (DQA and DQPA) H L H H H L Write Byte B – (DQB and DQPB) H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQD and DQPD) H
PAGE 11
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F IEEE 1149.1 Serial Boundary Scan (JTAG) Test Data-In (TDI) The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register.
PAGE 12
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls.
PAGE 13
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins.
PAGE 14
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels .................................................VSS to 3.3V Input pulse levels................................................ .VSS to 2.5V Input rise and fall times .................................................. 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.
PAGE 15
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Identification Register Definitions CY7C1386D/CY7C1386F CY7C1387D/CY7C1387F (512K × 36) (1M × 18) Instruction Field Revision Number (31:29) Description 000 000 01011 01011 Reserved for internal use. Device Width (23:18) 119-BGA 101110 101110 Defines the memory type and architecture. Device Width (23:18) 165-FBGA 000110 000110 Defines the memory type and architecture. Cypress Device ID (17:12) 100101 010101 Defines the width and density.
PAGE 16
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 119-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID F6 45 G4 67 L1 2 H4 T4 23 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 L5 28 E6 50 B3 72 L2 7 R6 29 D6 51 A3 73 8 U6 30 C7 52 C2 74 N2 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2
PAGE 17
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46
PAGE 18
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND ....... –0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ....
PAGE 19
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Capacitance [19] Parameter 100 TQFP Max. 119 BGA Max 165 FBGA Max Unit 5 8 9 pF 5 8 9 pF 5 8 9 pF Test Conditions 100 TQFP Package 119 BGA Package 165 FBGA Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 28.66 23.8 20.7 °C/W 4.08 6.2 4.
PAGE 20
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Characteristics Over the Operating Range [20, 21] Description Parameter tPOWER VDD(Typical) to the First Access [22] –250 Min –200 Max Min –167 Max Min Max Unit 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5.0 6.0 ns tCH Clock HIGH 1.7 2.0 2.2 ns tCL Clock LOW 1.7 2.0 2.2 ns Output Times tCO Data Output Valid after CLK Rise tDOH Data Output Hold after CLK Rise 1.0 1.3 1.3 ns tCLZ Clock to Low-Z [23, 24, 25] 1.0 1.
PAGE 21
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Waveforms Read Cycle Timing [26] tCYC CLK tCH t ADS tCL tADH ADSP t ADS tADH ADSC t AS ADDRESS tAH A1 A2 t WES GW, BWE,BW A3 Burst continued with new base address tWEH X t CES Deselect cycle tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data Out (DQ) High-Z CLZ t OEHZ Q(A1) t OEV t CO t OELZ t DOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t CO Single READ BURST READ DON’T CARE Burst wraps ar
PAGE 22
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Waveforms (continued) Write Cycle Timing [26, 27] t CYC CLK tCH t ADS tCL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for ﬁrst cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES tWEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t OEHZ DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 3) D(A3) D(A3 + 1) Data Out (Q) BURST READ
PAGE 23
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Waveforms (continued) Read/Write Cycle Timing [26, 28, 29] t CYC CLK tCL tCH t ADS tADH t AS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 t WES tWEH BWE, BW X t CES tCEH CE ADV OE t DS tCO Data In (D) t OELZ High-Z tOEHZ tCLZ Data Out (Q) tDH High-Z Q(A1) Q(A2) Back-to-Back READs D(A5) D(A3) Q(A4) DON’T CARE Q(A4+3) BURST READ Single WRITE D(A6) Back-to-Back WRITEs UNDEFINED Notes 28.
PAGE 24
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Waveforms (continued) ZZ Mode Timing [30, 31] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 30. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device. 31. DQs are in high-Z when exiting ZZ sleep mode. Document Number: 38-05545 Rev.
PAGE 25
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1386D-167AXC Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Operating Range Commercial CY7C1387D-167AXC CY7C1386F-167BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 26
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Ordering Information (continued) Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. 250 CY7C1386D-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1387D-250AXC CY7C1386F-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 27
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2.
PAGE 28
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Package Diagrams (continued) Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B Document Number: 38-05545 Rev.
PAGE 29
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Package Diagrams (continued) Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW TOP VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 MØ0.05 CAB MC PIN 1 CORNER Ø0.25 M C A B Ø0.50 -0.06 (165X) PIN 1 CORNER 1 2 1 +0.14 4 2 5 3 6 4 7 5 8 6 9 7 10 11 8 9 11 10 11 10 9 11 8 10 7 9 6 8 5 7 Ø0.50 -0.06 (165X) 4 6 3 +0.14 2 5 4 1 3 2 1A B A C B C B D C D C E D F 1.00 A 1.
PAGE 30
CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document History Page Document Title: CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F, 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM Document Number: 38-05545 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 254550 See ECN RKF New data sheet *A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for non-compliance with 1149.