Pipelined DCD Sync SRAM Specification Sheet

CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Document Number: 38-05545 Rev. *E Page 24 of 30
ZZ Mode Timing
[30, 31]
Switching Waveforms (continued)
t
ZZ
I
SUPPLY
CLK
ZZ
t
ZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
I
DDZZ
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
30. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device.
31. DQs are in high-Z when exiting ZZ sleep mode.
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