DDR-II SIO SRAM 2-Word Burst Architecture Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1393BV18

18-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

CY7C1392BV18, CY7C1992BV18

CY7C1393BV18, CY7C1394BV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05623 Rev. *D Revised June 2, 2008

Features

■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1392BV18 – 2M x 8

CY7C1992BV18 – 2M x 9

CY7C1393BV18 – 1M x 18

CY7C1394BV18 – 512K x 36

Functional Description

The CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and

CY7C1394BV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with Double Data Rate Separate IO (DDR-II SIO)

architecture. The DDR-II SIO consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. The DDR-II

SIO has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common IO devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

are latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K

. Read data

is driven on the rising edges of C and C if provided, or on the

rising edge of K and K

if C/C are not provided. Each address

location is associated with two 8-bit words in the case of

CY7C1392BV18, two 9-bit words in the case of

CY7C1992BV18, two 18-bit words in the case of

CY7C1393BV18, and two 36-bit words in the case of

CY7C1394BV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to the

two output echo clocks CQ/CQ

, eliminating the need to capture

data separately from each individual DDR-II SIO SRAM in the

system design. Output data clocks (C/C

) enable maximum

system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current x8 820 770 700 575 485 mA

x9 825 775 700 575 490

x18 865 800 725 600 500

x36 935 850 770 630 540

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Summary of content (31 pages)

PAGE 1
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description ■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock
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CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Logic Block Diagram (CY7C1392BV18) 20 K CLK Gen. DOFF LD LD Control Logic R/W C Read Data Reg. C CQ 16 R/W VREF Write Data Reg 1M x 8 Array K 1M x 8 Array Address Register Write Data Reg Read Add. Decode A(19:0) 8 Write Add. Decode D[7:0] 8 Control Logic 8 Reg. Reg. 8 Reg. 8 CQ 8 Q[7:0] NWS[1:0] Logic Block Diagram (CY7C1992BV18) 20 K CLK Gen. DOFF LD LD Control Logic R/W C Read Data Reg.
PAGE 3
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Logic Block Diagram (CY7C1393BV18) K K CLK Gen. DOFF LD LD Control Logic R/W C Read Data Reg. C CQ 36 R/W VREF 512K x 18 Array Address Register Write Data Reg Read Add. Decode 19 Write Data Reg 512K x 18 Array A(18:0) 18 Write Add. Decode D[17:0] 18 Control Logic 18 Reg. Reg. 18 Reg. 18 CQ 18 Q[17:0] BWS[1:0] Logic Block Diagram (CY7C1394BV18) K K CLK Gen. DOFF LD LD Control Logic R/W C Read Data Reg.
PAGE 4
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Pin Configuration The pin configuration for CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and CY7C1394BV18 follows. [1] 165-Ball FBGA (13 x 15 x 1.
PAGE 5
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Pin Configuration (continued) The pin configuration for CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and CY7C1394BV18 follows. [1] 165-Ball FBGA (13 x 15 x 1.
PAGE 6
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Pin Definitions Pin Name IO Pin Description D[x:0] InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. Synchronous CY7C1392BV18 - D[7:0] CY7C1992BV18 - D[8:0] CY7C1393BV18 - D[17:0] CY7C1394BV18 - D[35:0] LD InputSynchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition Synchronous includes address and read/write direction.
PAGE 7
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Pin Definitions Pin Name (continued) IO Pin Description CQ Echo Clock CQ is Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks is shown in the Switching Characteristics on page 23. CQ Echo Clock CQ is Referenced with Respect to C.
PAGE 8
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Functional Overview The CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and CY7C1394BV18 are synchronous pipelined Burst SRAMs equipped with a DDR-II Separate IO interface. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks (C/C, or K/K when in single clock mode).
PAGE 9
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 DLL These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock it to the desired frequency.
PAGE 10
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Truth Table The truth table for CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and CY7C1394BV18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. L-H L L D(A + 0) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges.
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CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Write Cycle Descriptions The write cycle description table for CY7C1992BV18 follows. [2, 8] BWS0 K K L L–H – During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. L – L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. H L–H – No data is written into the device during this portion of a write operation.
PAGE 12
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
PAGE 13
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 IDCODE BYPASS The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state.
PAGE 14
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 0 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 0 0 1 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
PAGE 15
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 106 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [10, 11, 12] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.
PAGE 16
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold a
PAGE 17
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Identification Register Definitions Instruction Field Value CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 000 000 000 000 Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) Description Version number. 11010100010000101 11010100010001101 11010100010010101 11010100010100101 Defines the type of SRAM.
PAGE 18
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65
PAGE 19
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (all other inputs can be HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. ■ Provide stable DOFF (HIGH), power and clock (K, K) for 1024 cycles to lock the DLL.
PAGE 20
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch up Current....................................................
PAGE 21
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Electrical Characteristics (continued) DC Electrical Characteristics Over the Operating Range [12] Parameter IDD [19] Description VDD Operating Supply Test Conditions VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 200 MHz 167 MHz ISB1 Automatic Power Down Current Max VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC, Inputs Static 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Min Typ Max Unit (x8) 575 mA (x9) 575 (x18) 600
PAGE 22
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit 5 pF CIN Input Capacitance CCLK Clock Input Capacitance 6 pF CO Output Capacitance 7 pF 165 FBGA Package Unit 18.7 °C/W 4.5 °C/W TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V Thermal Resistance Tested initially and after any design or process change that may affect these parameters.
PAGE 23
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Switching Characteristics Over the Operating Range [20, 21] 300 MHz Cypress Consortium Parameter Parameter 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max Min Max Min Max VDD(Typical) to the First Access [22] tPOWER 278 MHz Description 1 1 1 1 1 ms tCYC tKHKH K Clock and C Clock Cycle Time 3.3 8.4 3.4 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns tKH tKHKL Input Clock (K/K; C/C) HIGH 1.32 – 1.4 – 1.6 – 2.0 – 2.
PAGE 24
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Switching Characteristics (continued) Over the Operating Range [20, 21] 300 MHz Cypress Consortium Parameter Parameter 278 MHz 250 MHz 200 MHz 167 MHz Description Unit Min Max Min Max Min Max Min Max Min Max Output Times – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns – –0.45 – –0.45 – –0.45 – –0.50 – ns – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns 0.
PAGE 25
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Switching Waveforms Figure 5.
PAGE 26
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 300 Ordering Code CY7C1392BV18-300BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
PAGE 27
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Ordering Information (continued) Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Ordering Code CY7C1392BV18-250BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
PAGE 28
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Ordering Information (continued) Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1392BV18-167BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
PAGE 29
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER Ø0.50 -0.06 (165X) +0.14 1 2 3 4 5 6 7 8 9 10 11 11 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D E F F G G H J 14.00 E 15.00±0.10 15.00±0.10 10 H J K L L 7.00 K M M N N P P R R A A 1.00 5.00 10.00 B B 13.00±0.10 13.00±0.10 1.40 MAX. 0.15 C 0.53±0.05 0.
PAGE 30
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document History Page Document Title: CY7C1392BV18/CY7C1992BV18/CY7C1393BV18/CY7C1394BV18, 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number: 38-05623 Rev. ECN No.
PAGE 31
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document History Page Document Title: CY7C1392BV18/CY7C1992BV18/CY7C1393BV18/CY7C1394BV18, 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number: 38-05623 *D 2511728 06/03/08 VKN/PYRS Updated Logic Block diagrams Updated IDD/ISB specs Added footnote# 19 related to IDD Updated power up sequence waveform and its description Changed DLL minimum operating frequency from 80 MHz to 120 MHz Changed ΘJA spec from 28.51 to 18.