DDR-II SIO SRAM 2-Word Burst Architecture Specification Sheet
CY7C1392BV18, CY7C1992BV18
CY7C1393BV18, CY7C1394BV18
Document #: 38-05623 Rev. *D Page 23 of 31
Switching Characteristics
Over the Operating Range
[20, 21]
Cypress
Parameter
Consortium
Parameter
Description
300 MHz 278 MHz 250 MHz 200 MHz 167 MHz
Unit
Min Max Min Max Min Max Min Max Min Max
t
POWER
V
DD
(Typical) to the First Access
[22]
11111ms
t
CYC
t
KHKH
K Clock and C Clock Cycle Time 3.3 8.4 3.4 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns
t
KH
t
KHKL
Input Clock (K/K; C/C) HIGH
1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns
t
KL
t
KLKH
Input Clock (K/K; C/C) LOW
1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns
t
KHKH
t
KHKH
K Clock Rise to K Clock Rise and C
to C
Rise (rising edge to rising edge)
1.49 – 1.6 – 1.8 – 2.2 – 2.7 – ns
t
KHCH
t
KHCH
K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)
01.4501.5501.802.202.7ns
Setup Times
t
SA
t
AVKH
Address Setup to K Clock Rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
t
SC
t
IVKH
Control Setup to K Clock Rise
(LD
, R/W)
0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
t
SCDDR
t
IVKH
Double Data Rate Control Setup to
Clock (K/K
) Rise
(BWS
0
, BWS
1
,
BWS
2
, BWS
3
)
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
t
SD
[23]
t
DVKH
D
[X:0]
Setup to Clock (K/K) Rise
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Hold Times
t
HA
t
KHAX
Address Hold after K Clock Rise
0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
t
HC
t
KHIX
Control Hold after K Clock Rise
(LD, R/W)
0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
t
HCDDR
t
KHIX
Double Data Rate Control Hold after
Clock (K/K
) Rise
(BWS
0
, BWS
1
, BWS
2
, BWS
3
)
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
t
HD
t
KHDX
D
[X:0]
Hold after Clock (K/K) Rise
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Notes
21. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
22. This part has a voltage regulator internally; t
POWER
is the time that the power must be supplied above V
DD
minimum initially before a read or write operation can be
initiated.
23. For D2 data signal on CY7C1992BV18 device, t
SD
is 0.5 ns for 200 MHz, 250 MHz, 278 MHz, and 300 MHz frequencies.
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