Pipelined Sync SRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1442AV33

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined Sync SRAM

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05383 Rev. *E Revised June 23, 2006

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V/3.3V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• CY7C1440AV33, CY7C1442AV33 available in lead-free

100-pin TQFP package, lead-free and non-lead-free

165-ball FBGA package. CY7C1446AV33 available in

lead-free and non-lead-free 209-ball FBGA package

• Also available in lead-free packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Functional Description

[1]

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM

integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and

), Burst

Control inputs (ADSC

, ADSP, and ADV), Write Enables (BW

and BWE), and Global Write (GW). Asynchronous inputs

include the Output Enable (OE

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP

) or

Address Strobe Controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

LOW

causes all bytes to be written.

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33

operates from a +3.3V core power supply while all outputs may

operate with either a +2.5 or +3.3V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.2 3.4 ns

Maximum Operating Current 475 425 375 mA

Maximum CMOS Standby Current 120 120 120 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

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Summary of content (31 pages)

PAGE 1
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V/3.3V I/O power supply • Fast clock-to-output times — 2.
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Logic Block Diagram – CY7C1440AV33 (1M x 36) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND Q0 LOGIC ADSC ADSP BWD DQD ,DQPD BYTE WRITE REGISTER DQD ,DQPD BYTE WRITE DRIVER BWC DQC ,DQPC BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE DRIVER BWB BWA BWE GW CE1 CE2 CE3 OE ZZ MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQPA DQPB DQPC DQPD DQA ,DQPA BYTE
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Logic Block Diagram – CY7C1446AV33 (512K x 72) ADDRESS REGISTER A0, A1,A A[1:0] MODE Q1 BINARY COUNTER CLR Q0 ADV CLK ADSC ADSP BWH DQH, DQPH WRITE DRIVER DQH, DQPH WRITE DRIVER BWG DQF, DQPF WRITE DRIVER DQG, DQPG WRITE DRIVER BWF DQF, DQPF WRITE DRIVER DQF, DQPF WRITE DRIVER BWE DQE, DQPE WRITE DRIVER DQ E, DQP BYTE “a”E WRITE DRIVER BWD DQD, DQPD WRITE DRIVER DQD, DQPD WRITE DRIVER BWC DQC, DQPC WRITE DRIVER DQC, DQPC WRITE DRIVER MEMORY ARRA
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Configurations VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1442AV33 (2M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 4
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Definitions (continued) Name I/O Description CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ package version.
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Functional Overview then the Write operation is controlled by BWE and BWX signals. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6ns (250-MHz device).
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description IDDZZ
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Truth Table (continued)[2, 3, 4, 5, 6, 7] Operation Add.
PAGE 11
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Truth Table for Read/Write[4, 8, 9] Function (CY7C1446AV33) GW BWE Read H H X Read H L All BW = H Write Byte x – (DQx and DQPx) Write All Bytes H L L H L All BW = L Write All Bytes L X X IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port (TAP) The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with IEEE Standard 1149.1. The TAP operates using JEDEC-standard 3.
PAGE 12
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Performing a TAP Reset TAP Instruction Set A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. Overview At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry.
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 The boundary scan register has a special bit located at, bit #89 (for 165-FBGA package) or bit #138 (for 209-FBGA package). When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus.
PAGE 14
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 TAP AC Switching Characteristics Over the operating Range[10, 11] Parameter Description Min. Max.
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.135 to 3.6V unless otherwise noted)[12] Parameter VOH1 Description Test Conditions Output HIGH Voltage VOH2 Output HIGH Voltage VOL1 Output LOW Voltage VOL2 Output LOW Voltage VIH 2.4 V 2.0 V IOH = –100 µA VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 V IOL = 8.0 mA VDDQ = 3.3V 0.4 V IOL = 1.0 mA VDDQ = 2.5V 0.4 V VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Identification Codes (continued) Instruction Code Description SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
PAGE 17
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 209-ball FBGA Boundary Scan Order [14, 16] CY7C1446AV33 (512K x 72) Bit # ball ID Bit # ball ID Bit # 1 W6 36 F6 71 ball ID Bit # ball ID K3 72 H6 C6 106 2 V6 U6 37 K8 3 38 K9 107 K4 73 B6 108 K6 4 W7 39 5 V7 40 K10 74 A6 109 K2 J11 75 A5 110 L2 6 U7 41 J10 76 B5 111 L1 7 T7 42 H11 77 C5 112 M2 8 V8 43 H10 78 D5 113 M1 9 U8 44 G11 79 D4 114 N2 10 T8 45 G10 80 C4 115 N1 11 V9 46 F1
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.................................
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Capacitance[19] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 100 TQFP Max. 165 FBGA 209 FBGA Max. Max. Unit 6.5 7 5 pF 3 7 5 pF 5.5 6 7 pF 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit 25.21 20.8 25.31 °C/W 2.28 3.2 4.
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Switching Characteristics Over the Operating Range [24, 25] –250 Parameter tPOWER Description Min. [20] VDD(Typical) to the first Access –200 Max Min. –167 Max. Min. Max Unit 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5 6 ns tCH Clock HIGH 1.5 2.0 2.4 ns tCL Clock LOW 1.5 2.0 2.4 ns Output Times tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise [21, 22, 23] 2.6 1.0 3.2 1.5 1.
PAGE 21
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Switching Waveforms Read Cycle Timing[26] t CYC CLK t CH t ADS t CL t ADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 tWES A3 Burst continued with new base address tWEH GW, BWE, BWx tCES Deselect cycle tCEH CE tADVS tADVH ADV ADV suspends burst.
PAGE 22
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Switching Waveforms (continued) Write Cycle Timing[26, 27] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Ou
PAGE 23
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Switching Waveforms (continued) Read/Write Cycle Timing[26, 28, 29] tCYC CLK tCL tCH tADS tADH tAS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) tWES tWEH BWE, BWX tCES tCEH CE ADV OE tDS tCO tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) Q(A2) Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 28.
PAGE 24
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Switching Waveforms (continued) ZZ Mode Timing[30, 31] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 31. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05383 Rev.
PAGE 25
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1440AV33-167AXC Package Diagram Operating Range Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.
PAGE 26
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Ordering Code CY7C1440AV33-250AXC Package Diagram Operating Range Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.
PAGE 27
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Package Diagrams 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2.
PAGE 28
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Package Diagrams (continued) 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Package Diagrams (continued) 209-ball FBGA (14 x 22 x 1.76 mm) (51-85167) 51-85167-** i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05383 Rev. *E Page 29 of 31 © Cypress Semiconductor Corporation, 2006.
PAGE 30
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Document History Page Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Document Number: 38-05383 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 124437 03/04/03 CJM New data sheet *A 254910 See ECN SYT Part number changed from previous revision.
PAGE 31
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Document Number: 38-05383 REV. ECN NO. Issue Date Orig. of Change *E 473650 See ECN VKN Document #: 38-05383 Rev. *E Description of Change Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table.